Accellera

Defining and Advancing EDA and IP Standards

[Accellera @accellera]

New! The 1st video in Accellera’s “Learning PSS” series is now available. Presented by Portable Stimulus expert Tom Fitzpatrick, this introductory session provides an overview of PSS and the verification challenges it helps address. Watch: https://t.co/1fTfPwd2CP #Accellera #EDA

[Accellera @accellera]

At DVCon U.S. 2026, Accellera Chair Lu Dai spoke with Bernard Murphy to share the latest Accellera updates, including the newly released Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 Read the full article https://t.co/12ksZ0d14R #SystemC #EDA

[Accellera @accellera]

Be part of advancing the SystemC ecosystem! Join Accellera’s new SystemC Sprint April 22 in Aachen, Germany, followed by the online SystemC Evolution Fika April 23. Scan the QR codes to learn more. For more information on SystemC visit https://t.co/4SJcutwhKt #Accellera #SystemC

[Accellera @accellera]

Applications are open through April 30 for Accellera's Stanley J. Krolikoski Scholarship supporting undergraduate students pursuing degrees in EE & CS. Please share if you know of a student that may be interested https://t.co/YxtbDlNxIK. #EDA #EE #Verification #Accellera.

[Accellera @accellera]

Accellera Board Approves CDC/RDC Standard 1.0 For Immediate Release!
The Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 is now available for download. Read the full press release here: https://t.co/ezc15rtmdU #CDC/RDC #EDA #Accellera

[Accellera @accellera]

Join Accellera for a workshop “IP-XACT Demystified: An in-depth training on the IEEE 1685-2022 IP-XACT Standard” March 5 at DVCon U.S. & gain a practical understanding of IP-XACT and how to apply it in real SoC projects https://t.co/UNKTLKN2cr #IP-XACT #DVCon_US #EDA #SoC

[Accellera @accellera]

Check out the latest newsletter from Accellera to see what’s ahead for attendees at DVCon U.S. 2026. Hear updates from our IP-XACT, Portable Stimulus (PSS), CDC and SystemC Working Groups, learn about our new SystemC Sprint event, and explore much more https://t.co/iFo3RWGXIT

[Accellera @accellera]

Accellera has an exciting lineup planned for DVCon U.S.! Join us for workshops on PSS, IP-XACT, and SystemC, plus a tutorial on CDC/RDC. We’ll also be hosting a reception on March. Learn more in https://t.co/U5L1hNYDDJ https://t.co/acvQw656B0

#Accellera #DVConUS #EDA

[Accellera @accellera]

Accellera Chair Lu Dai chats with Bill Wong of @ElectronicDesign to explore Accellera’s pivotal role in the EDA ecosystem, the real-world impact of its standards, and what’s ahead for the industry. Read the interview here https://t.co/aDswU9cRIy #Accellera #EDA #AI #IEEE

[Accellera @accellera]

Are you a chip architect navigating next-generation SoC complexity or a tool developer enabling the next gain in automation? Check out the blog by Daniel Payne in SemiWiki, “Boosting SoC Design Productivity with IP-XACT” https://t.co/3bUPuhj9wR #Accellera #EDA #IP #SoC

[Accellera @accellera]

Accellera’s Portable Stimulus Working Group Chair, Matthew Ballance, offers an inside look at the enhancements in 3.1 and how they will further accelerate verification productivity across the industry. https://t.co/Ga4yhKDgyM #EDA #PSS #Accellera #SoC

[Accellera @accellera]

Discover new videos, get the latest on upcoming events worldwide, and catch up on working group progress in Accellera’s August newsletter! https://t.co/IVcseBTMbT #EDA #DVCon #verification

[Accellera @accellera]

New Video Available! “Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration” presented at DVCon U.S. 2025
View on Accellera’s YouTube Channel https://t.co/jOg1B2SKDz #UVM #Accellera #IEEE

[Accellera @accellera]

Inside Scoop on AI in EDA! Bernard Murphy recaps Accellera's panel at #62DAC in his latest SemiWiki article. Hear what experts from AMD, Cadence, Microsoft, NVIDIA, Siemens, and Synopsys had to say about AI’s impact on design and verification https://t.co/aC77KENeOu
#AI #EDA

[Accellera @accellera]

Exciting insights from Lu Dai, Chair of Accellera, in a conversation with Sanjay Gangal as they discuss Accellera’s upcoming luncheon focused on AI in Design and Verification at #62DAC and more! See the video @Sanjaytechcafe on YouTube https://t.co/wDDVvUdk47 #EDA #AI

[Accellera @accellera]

Interested in the latest SystemC developments & applications? Join the free virtual workshop, the SystemC Evolution Fika, on June 26 16:00-18:00 CET. Register: https://t.co/uBx8hHv9xS. More info, and presentations from past Fikas, visit https://t.co/MXODT2cCay #SystemC #Accellera

[Accellera @accellera]

Join Accellera @ #62DAC for a lunch panel discussion, “Can AI Cut Costs in Electronic Design and Verification While Accelerating Time-to-Market?” on Tuesday, June 24 at noon; It's free to attend, but registration is required https://t.co/gJkVR4mtPA #AI #design #verification #EDA

[Accellera @accellera]

NEW VIDEO! Explore the latest enhancements to IEEE 1801™-2024 (UPF 4.0) in the workshop from DVCon U.S. 2025 now available to view on demand! Watch now on Accellera's YouTube channel: https://t.co/62QJNUCEXa

#IEEE #Accellera #UPF #LowPowerDesign #DVCon_US #IP

[Accellera @accellera]

Explore AI’s Impact on Design and Verification with Accellera's panel of experts at #62DAC on Tuesday, June 24 at noon; It's free to attend, but registration is required https://t.co/gJkVR4lW02 #AI #design #verification #EDA

[Accellera @accellera]

Check out what Accellera is up to @ the 62nd DAC, the launch of the SystemC Summer of Code Program, free access to IEEE 1801-2024 via the GET Program, and so much more in the May Accellera newsletter. Check it out https://t.co/ydRBNQhPeu #Accellera #SystemC #DVCon #IEEE #62DAC