RISC-V International

RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.

[RISC-V International @risc_v]

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: https://t.co/JvDqgRiubQ

[RISC-V International @risc_v]

Your ideas belong on the RISC-V Summit stage. The Call for Papers for RISC-V Summit North America 2027 closes October 30 at 11:59 PM PDT.

Have something to share? Submit a:
• 20-min Session Presentation
• 40-min Deep Dive
• 40-min Panel
• Poster

Topics span AI/ML, security, automotive, robotics, HPC, software, core design, custom compute and more.

Submit your proposal by October 30: https://t.co/3yeX41ll6K

#RISCV #CallForPapers #RISCVSummit

[RISC-V International @risc_v]

Can your software survive a kernel attack?

Watch the recording of “Hands-on OP-TEE Security with Andes RISC-V”, presented by Paul Shan-Chyun Ku.

Learn how to:
• Build secure applications with OP-TEE
• Use ePMP and IOPMP for hardware isolation
• Protect sensitive data from kernel and DMA attacks
• See real attack-and-defense scenarios on RISC-V

Whether you're building secure embedded systems or exploring trusted execution environments, this workshop offers a practical introduction to hardware-backed security on RISC-V.

🎥 Watch the recording: https://t.co/48DOnbVqfD

[RISC-V International @risc_v]

What does #RISCV look like in high-performance computing? 👀
In just two minutes, Emanuele Venieri walks us through the Monte Cimone v3 project and its evaluation of RISC-V for #HPC clusters.
Based on the Sophon SG2044 processor, Monte Cimone v3 was tested using HPL and STREAM benchmarks, with performance and power measurements compared against Intel Xeon Platinum 8480+ and @NVIDIA Grace CPU Superchip platforms.
Watch the poster walkthrough, then explore the full project to dive deeper into the results.
👉 Check out this project: https://t.co/SSNMy2mYxN

[RISC-V International @risc_v]

There are plenty of ways to contribute to the RISC-V community.

Our Advocates are organizing events, sharing knowledge, building technical communities, supporting education, and growing RISC-V in new regions.

In this Advocate Spotlight, meet four people taking different approaches to advocacy:
🔹 Guodong Xu: connecting RISC-V standards with real-world adoption
🔹 Tobias Scheipel: building, teaching, and growing the community
🔹 Jingwei Wang: supporting the RISC-V software ecosystem
🔹 Tan Siret Akinci: growing RISC-V in Turkey

See what they’re doing, find something that inspires you, and get involved.

👉 Read the full story: https://t.co/sZRkkWzNYO

[RISC-V International @risc_v]

Every bug tells a story, if you have the right tools to find it.

The recording of “Advanced Debug and Trace Tools for RISC-V Architectures” is now available.

In this interactive workshop, Maurizio Menegotto (Lauterbach) walks through advanced debugging workflows using TRACE32, including live demonstrations on both 64-bit and 32-bit RISC-V systems.

Follow along to explore:
• Multicore debugging techniques
• Long-term real-time trace
• Linux OS debugging on RISC-V
• Interactive debugging on 32-bit RISC-V cores
• Practical workflows for tracking down complex software bugs

Whether you're new to TRACE32 or looking to improve your debugging workflow, this session is packed with practical demonstrations and expert guidance.

🎥 Watch the recording: https://t.co/XmGHINc0wq

#RISCVDeveloperWorkshops

[RISC-V International @risc_v]

From prototype to Linux-powered microserver.

Building new RISC-V hardware is only part of the challenge. Getting storage, networking, firmware, and software working together is where the real integration begins.

This Featured Work highlights the RISER Microserver Platform and shares lessons learned while bringing up a standalone RISC-V system designed for cloud and accelerator research.

Explore the project and discover what the team learned along the way: https://t.co/hcLFC8sB2H
#RISCVFeaturedWork

[RISC-V International @risc_v]

Come see what people in the community are building on RISC-V.

Join our YouTube live tomorrow, Wednesday, September 23 at 8AM PDT (5PM CEST), as Tobias (TU Graz) and Bernd (TU Graz) talk about how they turned HaDes-V, a teaching project, into Tartarus, a RISC-V system capable of running DOOM.

They’ll cover:
• What it took to get DOOM running, from CPU extensions and memory to graphics, input, and audio
• The bottlenecks, debugging challenges, and unexpected problems along the way
• What they learned about RISC-V, processor design, and using real workloads in education
• What they might build next

Bring your questions and join us live, or catch the recording on YouTube afterward.
https://t.co/BMxC5ylcVY

#RISCVBuilders

[RISC-V International @risc_v]

RISC-V Summit North America 2027 website is now available to explore, with event details and information for attendees and speakers.

Planning to submit a talk? Explore the Call for Papers for suggested topics, submission types, key dates, and speaker requirements. Submissions will open soon, with proposals due by October 30, 2026.

Hyatt Regency Embarcadero, San Francisco
February 16: Member Day | February 17–18: Main Conference

Learn more: https://t.co/FOhxBpqHNb

#RISCVSummit #RISCVEverywhere

[RISC-V International @risc_v]

What are people actually building with RISC-V?

Discover “RISC-V Builders”, a YouTube Live series where the people behind a project get together to talk about what they built, how they built it, and what they learned along the way.

Our first episode will cover: How a student-built RISC-V processor went from teaching core to running DOOM.

Join Tobias Scheipel (TU Graz) & Bernd Stelzl (TU Graz) live on Wednesday September 23 at 8AM PDT: https://t.co/llNGZ3NKrO

Set a reminder and bring your questions! #RISCVBuilders

[RISC-V International @risc_v]

For automakers, RISC-V isn’t just about ownership. It’s about freedom of choice.

@mips_riscv Sameer Wasson explains why choosing an ISA should prioritize supplier choice, software reuse and long-term economic control.

Read more: https://t.co/p224RnAFI5

#RISCV #Automotive

[RISC-V International @risc_v]

🚗 We’re onsite at #AutoWorldJapan! 🇯🇵

RISC-V is giving the automotive industry greater flexibility and control over the silicon roadmap, from architecture to software.

Stop by Booth A4-36 at Makuhari Messe to explore the RISC-V automotive ecosystem and chat with our team about what’s next.

#RISCV #Automotive

[RISC-V International @risc_v]

Want to debug Zephyr RTOS on real RISC-V hardware?
Watch the recording of “Zephyr RTOS Debugging and Performance Analysis on RISC-V”, presented by Maurizio Menegotto and Benjamin Cabé.
Learn how to:
• Set up a Zephyr development environment
• Build, flash, and debug Zephyr applications
• Analyze thread behavior and system performance
• Use TRACE32 for kernel-aware debugging on RISC-V
Whether you're developing embedded applications or working with Zephyr RTOS, this workshop offers practical debugging techniques you can apply right away.
🎥 Watch the recording: https://t.co/QhCyzV3ygH

[RISC-V International @risc_v]

Who controls your silicon roadmap? 🚗

With RISC-V, automakers can take greater control from architecture to software.

Next week at #AutoWorldJapan 🇯🇵

📍 Booth A4-36
🎤 CEO Andrea Gallo: The Open Road: Control your silicon roadmap with RISC-V
📅 Sept. 9 | 16:00–16:30

See you in Japan!

[RISC-V International @risc_v]

What does it take to build a RISC-V cloud server?

The latest Featured Work takes you inside the RISER project, where researchers are developing an all-European RISC-V microserver platform capable of running a full Linux software stack.
Learn how the team integrated FPGA prototyping, boot firmware, NVMe storage, and 100 Gbps Ethernet, along with the challenges they faced bringing the platform to life.
Read the full Featured Work and see what others are building on #RISCV: https://t.co/gOSB4l6ssk
#RISCVFeaturedWork

[RISC-V International @risc_v]

See what the finalists from the #RISCVCommunityChallenge built with HaDes-V.

🎥 The recording is now available. Take a look at what the community has been building and researching: https://t.co/pSOKtXhdUM (https://t.co/pSOKtXhdUM)

#RISCV #HaDesV

[RISC-V International @risc_v]

Imagine you're handed a RISC-V system and challenged to turn it into a secure, multi-guest virtualized platform.

That's exactly what participants tackled in this hands-on developer workshop.
Working with the Bao hypervisor on a CVA6-based platform, Sandro Pinto (OSYX Technologies) and Joerg Seitter (Infineon Technologies AG) guide you through the process of partitioning software, isolating workloads, and building the foundation for future automotive systems.

The full recording is now available, so you can follow the workshop at your own pace and see how virtualization works in practice, not just in theory.

🎥 Watch the recording: https://t.co/EsJc1q4T8W
#RISCVDeveloperWorkshops

[Brendan Burke @BrendanBurkeX]

Krste, Chief Architect @SiFive fit all the 40 instructions from the base @risc_v ISA on a slide at Hot Chips.

Vector extensions are mandatory in RVA23 profile and four different matrix extensions are approaching ratification.

That unlocks AI use cases from edge to cloud with a common ISA.

Krste's theory: RISC-V accelerators will combine GPU and CPU functions on the same chip. "Something that people might be looking at as well."

Server CPU is the next opportunity for the community with a new Server Platform Spec. Server-class RISC-V silicon is loading. Will be interesting to see how it supplements the shift to Arm.

[RISC-V International @risc_v]

Can AI help modernize custom RISC-V extensions?

In this month's Featured Work, researchers demonstrate an end-to-end workflow that uses AI to identify instruction conflicts, propose compliant opcode mappings, and automatically generate the hardware and software needed to bring those changes to life.

The result is a fully working open-source stack spanning RTL, toolchains, Zephyr support, simulation, and application code, showing how AI can reduce the effort involved in evolving RISC-V processor designs.

Explore the project and see what's possible: https://t.co/W9DMHOzd8s