RISC-V International

RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.

[RISC-V International @risc_v]

The RISC-V Developer Workshops have exceeded all expectations! We sold out, added more seats, and the Hardware Track sold out again. Only a few seats remain for the Software Track.
🎟️ Grab one of the remaining Software Track seats before they're gone! https://t.co/u49RoyuioF
Want to stay in the loop about future Developer Workshops and other “Learn RISC-V” opportunities?
✍️Sign up for the RISC-V Education Newsletter: https://t.co/JvGgjs13rk

[RISC-V International @risc_v]

The #RISCVcommunity grows because of people who step up and share their time, knowledge, and energy with others.

This year, we welcomed a few new RISC-V Advocates, and they’ve already made a strong impact across the ecosystem. We also want to recognize the advocates who have continued their journey in the program through their ongoing contributions.

Being a #RISCVAdvocate is about helping others learn, connect, and get involved. Whether you're looking for local meetups, educational resources, or fellow community members in your region, our advocates are helping make RISC-V more accessible around the world.

Find and connect with your local advocate: https://t.co/0F2C3YdfQk

Thank you to all of our advocates for everything you do for the RISC-V ecosystem 💙

[RISC-V International @risc_v]

Before RISC-V Summit starts... Get hands-on with the RISC-V Community!

Join us on Monday 8 June in Bologna for a full day of learning, workshops, and community events before RISC-V Summit Europe officially begins.

Whether you're new to RISC-V or already building on it, there’s something for you:

🔹 Intro to RISC-V (Open to the public, with no fee)
🕘 9:30–13:00
Come hear about the What, How and Why of RISC-V.
Save your seat: https://t.co/YWKXVqByxF

🔹 HaDes-V Community Challenge (Free Event)
🕑 14:00–17:30
Get hands-on with RISC-V processor design and FPGA-based learning while exploring how modular 32-bit RISC-V microcontrollers run on real hardware.
The workshop is free to attend, register here: https://t.co/AfXtZE1QUs

🔹 RISC-V Developer Workshops (Almost Sold Out)
🕘 8:30–18:00
Full-day hands-on workshops (€30)
Experiment with tools, test what works today, and see how hardware and software can be co-designed.
Secure your seat: https://t.co/4eyr6evHFX

📍 Bologna • Palazzo dei Congressi
Come early. Learn something new. Meet the community before Summit week begins.

[RISC-V International @risc_v]

Developers, roll up your sleeves! Join us in person for a full day of hands-on #RISCV workshops. Open to all with a €30 pass.

#RISCVDeveloperWorkshops

📅 Monday 8 June 2026
⏰ 8:30 - 18:00
📍 Palazzo dei Congressi, Bologna, Italy
🎟️ €30 pass

👉Seats are limited to ensure maximum interaction. Reserve yours now: https://t.co/XdMrgMprVh

[RISC-V International @risc_v]

See the agenda for the #RISCVDeveloperWorkshops 👇
#Software Track:
💻Advanced debug and trace tools for RISC-V architectures
Speaker: Maurizio Menegotto | Lauterbach

💻TBA
Speakers: Maurizio Menegotto | Lauterbach and Benjamin Cabe | Zephyr Project

💻Hands-on OP-TEE with Andes RISC-V
Paul Shan-Chyun Ku | Andes

💻Porting SIMD to RISC-V Vectors
Speaker: Daniel Thompson | RISCstar Solutions

💻Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline
Speakers: Niraj Dengale and Frank, Yueh-Feng Lee | Andes Technologies

💻How to: Bringing up ExecuTorch on a RISC-V Microcontroller
Speaker: Jeremy Bennett | Embecosm

#Hardware Track:
🔧From Open Silicon to Real Hardware: Hands-On RISC-V Development with Zephyr and the Puppy Microcontroller
Speakers: Marcelo Knorich Zuffo and Laisa Costa De Biase | Universidade de Sao Paulo

🔧Building an AI Accelerator with High-Level Synthesis
Speaker: Werner Bachhuber | Siemens EDA

🔧UCAgent: An End-to-End Agent for Unit-Level Chip Verification
Speaker: Junyue Wang | Institute of Computing Technology, CAS

🔧RISC-V Architectural Certification Tests Early Adoption workshop
Speakers: Jordan Carlin, David Harris | Harvey Mudd College and Mike Thompson | OpenHW Foundation

🔧Hands-on Introduction to CHERI
Speaker: Alfredo Mazzinghi | CHERI Alliance

🔧Introduction to RISC-V in gem5
Speaker: Ivan Fernandez Vega | Barcelona Supercomputing Center

🔧Building a Multi‑Guest Virtualized System with Bao on CVA6 in Automotive
Speakers: Joerg Seitte | Infineon Technologies AG and Sandro Pinto | OSYX Technologies

Grab your ticket 👉 https://t.co/CFonaYYXg6

[RISC-V International @risc_v]

#OSSSummit is bustling! With a few more days to go, there's still time to register and attend the RISC-V Insights Mini Summit and stop by our booth (B8)!

Sign up > https://t.co/R0eaNwCZ49

#RISCV #RISCVEverywhere

[RISC-V International @risc_v]

Shipping fast matters. Shipping natively matters more.

A new community effort brings Docker v29 to RISC-V64 in just 6 days after release. Built entirely on RISC-V hardware, these automated pipelines deliver a complete, production-ready container stack, as .deb and .rpm packages, with full feature parity.

Engine. CLI. Compose. Buildx. All there.

No special cases. No compromises.

This milestone shows how quickly RISC-V is closing the gap and, in some cases, setting the pace.

Take a look at the full story behind this Featured Work and see what’s possible today.
https://t.co/dKlb4OR6rU

[RISC-V International @risc_v]

The RISC-V Insights Mini Summit will take place on May 21, from 9am-12:30pm, its ONLY $20 and requires a separate registration. Learn more > https://t.co/R0eaNwCZ49

[RISC-V International @risc_v]

We’ll be at #OSSummit + #EmbeddedLinux Conference North America, May 18–20 🌍 and we're hosting a RISC-V Insights Mini Summit on the 21st (that's next Thursday!)

This is THE spot to connect with open source enthusiasts, discover emerging trends, and get inspired by what’s next in the ecosystem.

Schedule ➡️ https://t.co/T3G8L13HVr
🎟️ Register now: https://t.co/v9u4Bb4Scg

#RISCV #RISCVEverywhere

[DeepComputing @DeepComputingio]

The DC-ROMA RISC-V Mainboard III for #Framework Laptop 13 is now open for preorder: https://t.co/MMlmFPUiDZ
Powered by the SpacemiT K3:
• RVA23 support — a major milestone for Linux standardization
• Up to 60 TOPS AI compute
• Ubuntu & Fedora support
This isn’t just another dev board — it’s a usable RISC-V laptop.
#RISCV #OpenSource #Linux #Ubuntu #Fedora #DCROMA

[RISC-V International @risc_v]

From edge AI to advanced debugging and tracing.
From Zephyr to porting software to RISC-V.
From automotive software isolation to developing and running compliance testing.

The first European #RISCVDeveloperWorkshops bring it all together in one place, through hands-on labs.

If you want practical experience, this is where it happens 👉Join hands-on Developer Workshops on June 8 in Bologna, the day before RISC-V Summit Europe.

Open to all. €30 for a full day. Limited seats available, so grab yours quickly.

Register today: https://t.co/ZI0j2fdOz2

[RISC-V International @risc_v]

Get paid while you learn!

RISC-V mentorships are open, and they are paid.

You will work on a focused project with a RISC-V Member Organization, build practical skills, meet people in the field, and walk away with something you can actually show.

📅 Program runs from June 1 to August 31, 2026
📝 Deadline to apply: May 17, 2026

Explore the available mentorships here:
https://t.co/HXK2F57FQN

#RISCVmentorship #LearnRISCV #RISCV #jobopenings

[RISC-V International @risc_v]

Coming to #RISCV Summit Europe?
Arrive one day early.

On 8 June in Bologna, we’re running the #RISCVDeveloperWorkshops at Palazzo dei Congressi, just before the Summit.

This is a full day of hands-on, expert-led sessions across #hardware and #software.

On the agenda:

Hardware track:
- AI accelerators
- Test generation + running the ISA compliance test suites
- CHERI
- Executorch and TinyML pipelines on RISC-V

Software track:
- RISC-V Vectors
- Advanced debugging with Lauterbach
- Zephyr on RISC-V
- OP-TEE

€30 for the full day. Open to all. Limited seats available.

Save your spot 👉 https://t.co/0hR0oeItEr

[RISC-V International @risc_v]

Newest Featured Work – See what others are building on RISC-V
Docker on RISC-V is moving at a different pace now.

With community-maintained packages, Docker v29 is available on RISC-V64 within days of release, not months. Fully automated pipelines compile natively on RISC-V hardware and deliver the full stack as installable .deb and .rpm packages: Engine, CLI, Compose, and Buildx.

No workarounds. No missing features. Just parity.

This is what it looks like when a community gets ahead of the ecosystem.

Explore how it all came together and what it unlocks for developers working on RISC-V.

https://t.co/FuatB2LbpF

[RISC-V International @risc_v]

Hardware or Software?

Why not both.

Join us in Bologna on 8 June for the RISC-V Developer Workshops, happening the day before #RISCVSummitEurope.

We’re bringing hands-on, expert-led sessions across both tracks, so you can build, test, and learn by doing, not just listening.

€30 for a full day. Limited seats available.

Check out the agenda and save your spot 👉
https://t.co/4XqHPG7yHF

#RISCV #DeveloperWorkshops #Hardware #Software #RISCVDeveloperWorkshops

[RISC-V International @risc_v]

🚨 We’re live at Microelectronics today and tomorrow.

If you’re attending, make your way to Booth 430 and meet the team!

🎤 Don’t miss Tom Gall, our VP of Technology, speaking on RISC-V and the Future of Open Architectures. A must-attend session for anyone interested in what’s next for semiconductors, innovation, and open collaboration.

#RISCV #RISCVEverywhere

[RISC-V International @risc_v]

A full day to build, test, and learn RISC-V.

Join us on 8 June in Bologna for the RISC-V Developer Workshops, just before #RISCVSummitEurope.

We’re running hands-on sessions across both #software and #hardware tracks, led by experts from across the #RISCV ecosystem.

Just practical work, and things you can apply right away.

€30 for the full day. Limited seats available.

Save yours now! Register here 👉
https://t.co/U3tsunvupM

[RISC-V International @risc_v]

💡 Predict before you implement.

Thales built a precise performance model for the CVA6 RISC-V core to evaluate changes before touching RTL. The model achieved COREMARK performance results that were within 0.8% of the RTL, uncovering performance bottlenecks and informing the design of a dual-issue CVA6 core.

Outcome? A 40% performance boost with just +7% power and +11% area. This shows how modeling can transform open hardware development.

Explore the project here: https://t.co/AWwpjwFKMw

[RISC-V International @risc_v]

Curious about what you can actually build on RISC-V?
This is where things get hands-on.

Join us for a day of hands-on workshops designed for developers who want more than slides. You’ll experiment with tools, test what works today, and see how #hardware and #software can be co-designed.

We’re going all in on practical learning, direct application, and the chance to start building right away alongside experts and other developers and engineers.

Check out the #RISCVDeveloperWorkshops’s agenda, and join us! 😎
https://t.co/813M0UN4Ld
________________________________________________
🎟️ €30 pass | Open to all
📅 Monday 8 June 2026
📍 Palazzo dei Congressi, Bologna, Italy

#developers #RISCV #Bologna #RISCVSummitEurope

[RISC-V International @risc_v]

Looking for a way to gain real experience this summer?

RISC-V Member Organizations are offering paid mentorships where you can work on real-world projects, get exposure to industry teams, and learn by doing. And yes, you get paid while learning!

📅 Summer Program: June 1 to August 31, 2026
📝 Apply by: May 17, 2026

Take a look at the current opportunities and find the one that fits you:
https://t.co/vcWMJynNHp

#RISCVmentorship #LearnRISCV #RISCV #jobopenings