Ritvik Aggarwal

VLSI Engineer | ASIC Implementation (Fusion Compiler, Design Compiler) • Constraint Management | Sharing what I learn, one insight at a time!

[Ritvik Aggarwal @___Ritvik___]

👋 Hey, I'm Ritvik! On a journey to learn and explore VLSI, sharing concepts, insights, and everything I pick up along the way.
Dive in with me as I navigate the world of semiconductor design — one post at a time!

[Ritvik Aggarwal @___Ritvik___]

Constraint promotion and demotion sound simple in theory

But every constraint type follows its own set of translation rules across hierarchy..

🔗 Here's the full write-up : https://t.co/taBfVrIYA2

[Ritvik Aggarwal @___Ritvik___]

Constraint promotion and demotion sound simple in theory

But every constraint type follows its own set of translation rules across hierarchy..

🔗 Here's the full write-up : https://t.co/taBfVrIYA2

[Ritvik Aggarwal @___Ritvik___]

Promotion and Demotion aren’t just HR terms..

In chip design, they define how timing intent moves across hierarchy..

Here's the full write-up: https://t.co/UVP9a095eG

[Ritvik Aggarwal @___Ritvik___]

Promotion and Demotion aren’t just HR terms..

In chip design, they define how timing intent moves across hierarchy..

Here's the full write-up: https://t.co/UVP9a095eG

[Ritvik Aggarwal @___Ritvik___]

I didn’t realize I was using AI incorrectly..

Chances are, you might be too..

Here's the full write-up: https://t.co/7EZRiYE3Rv

[Ritvik Aggarwal @___Ritvik___]

What if you used a fake clock instead of an actual one to time your block?

This concept is not foreign and is widely employed for block timing.

Here's the full write-up: https://t.co/LzikGypsta

[Ritvik Aggarwal @___Ritvik___]

You know what timing constraints are, but are they good enough?

If these constraints are not "good" then the design also isn't.

Here's the full write-up: https://t.co/f1fDUSn1ZE

[Ritvik Aggarwal @___Ritvik___]

The clock looked clean, but a silent pulse slipped through..

The full article covers
• What a clock leak actually means
• Common causes for it
• Its consequences
• How are these identified during implementation
• Best practices to prevent them

https://t.co/kYQTSzPmez

[Ritvik Aggarwal @___Ritvik___]

Your I/O budgets aren't wrong - but they aren't the best either..
Why? Cause they are just estimates..

Here's the full write up: https://t.co/99mmevyQmk

[Ritvik Aggarwal @___Ritvik___]

What if you used a fake clock instead of an actual one to time your block?

This concept is not foreign and is widely employed for block timing.

Here's the full write-up: https://t.co/LzikGypsta

[Ritvik Aggarwal @___Ritvik___]

You know what timing constraints are, but are they good enough?

If these constraints are not "good" then the design also isn't.

Here's the full write up: https://t.co/f1fDUSn1ZE

[Ritvik Aggarwal @___Ritvik___]

Your I/O budgets aren't wrong - but they aren't the best either..
Why? Cause they are just estimates..

Here's the full write up: https://t.co/99mmevyQmk

[Ritvik Aggarwal @___Ritvik___]

The clock looked clean, but a silent pulse slipped through..

The full article covers
• What a clock leak actually means
• Common causes for it
• Its consequences
• How are these identified during implementation
• Best practices to prevent them

https://t.co/kYQTSzPmez

[Ritvik Aggarwal @___Ritvik___]

Check out my post on

Percentage Based I/O Budgeting : A Smart Start for Timing Closure

https://t.co/hMgFvSLJJd

[Ritvik Aggarwal @___Ritvik___]

Check out my post on

Percentage Based I/O Budgeting : A Smart Start for Timing Closure

https://t.co/hMgFvSLJJd

[Ritvik Aggarwal @___Ritvik___]

Check out my post on

Percentage Based I/O Budgeting: A Smart Start for Timing Chaos https://t.co/hMgFvSLJJd

#VLSI #ASICDesign #StaticTimingAnalysis #SoCDesign #PhysicalDesign

[Ritvik Aggarwal @___Ritvik___]

Check out my post on things I learnt as a Design Engineer Trainee:

https://t.co/7pi2wX0oUp

[Ritvik Aggarwal @___Ritvik___]

Check out my post on:
Timing Budgets at Block Boundaries : Why I/O Constraints Matter

https://t.co/IDaFLeToQZ

#VLSI #ASICDesign #StaticTimingAnalysis #SoCDesign #PhysicalDesign

[Ritvik Aggarwal @___Ritvik___]

Check out my post on Top-Down vs Bottom-Up design approach and methodology employed in chip design
https://t.co/sfxc1qyjco

[Ritvik Aggarwal @___Ritvik___]

Check out my post on Shift Left Methodology

https://t.co/A6S0TyXCig