Ajay

.....

[Ajay @AjaySabareesh24]

@TMobileHelp Missed refilling my prepaid account last night, lost service. Need assistance with reinstating the account.

[Ajay @AjaySabareesh24]

I will have published twice at ISSC/VLSI, finished the ironman, and play the guitar when I'm 25. Then I'll be back.

[Ajay @AjaySabareesh24]

Obviously hybrid hiding and masking is the future for security? But who's going to find the best way to do it?

[Ajay @AjaySabareesh24]

Cheap dopamine.

[Ajay @AjaySabareesh24]

These are smaller, more tangible goals compared to the HUGE scale of AURORA earlier. That still is the end goal, but considering my lack of expertise in compiler and system design, I just believed it was better to take the L and start small and specific.

[Ajay @AjaySabareesh24]

AURORA PIVOT
I think over the past couple of weeks, it was very clear to me that I do not have the expertise to be able to build the entire pipeline at one go or even start. The scale of PIM and its neverending complexities that change for every core was to overwhelming.

[Ajay @AjaySabareesh24]

So this stage of AURORA is a 2 step process
A: building a Data Dependency Graph from lowered instructions.
B: Creating a unified memory between Host and DPU using CXL to improve latency.

[Ajay @AjaySabareesh24]

I have to read them all.

[Ajay @AjaySabareesh24]

That would mean that AURORA will have to generate both the code and also the firmware, essentially generating a bare metal script based off of mathematical instructions and just a JSON file that describes the hardware. Difficult. I hope its not impossible though.

[Ajay @AjaySabareesh24]

One clear disadvantage and possibly the biggest problem developing the software stack for PIM is the lack of interest shown by hardware engineers like myself in making a usable ISA for the chip.

[Ajay @AjaySabareesh24]

OpenMP based portability relies mostly on the use of firmware developed by AMD and NVIDIA to be able to connect the 'target' construct with the pragma functions used in generic C++ code.

[Ajay @AjaySabareesh24]

Funny enough, since i've sat down and broken a PNM core into these characteristics, any new PNM paper I ever read, I will only judge it through the lense of the 6 pillars. PEAK.

[Ajay @AjaySabareesh24]

Its faily obvious that out of all the buckets (different PIM paradigms) Bucket D [ UPMEM, Tesseract] are the easiest to target because they are near memory processors and have a more standardised structure considering they are commercially available PIM chips.

[Ajay @AjaySabareesh24]

3. Communication : do tiles communicate? message passing? NO COMMS?

4. Parallelism Model : independent execution? banked ? SIMD/MIMD?

5. ISA/Legalisation : understand level of controller on chip and lower accordingly.

6. Cost Model : Compiler running blind otherwise.