Thrilled to announce that @naveen_venk and I have joined @join_ef to build @archgen_ .
Our thesis is simple:
The next generation of semiconductor design tools will not just automate workflows they will learn from every engineer who uses them.
Chip design today is full of repeated manual effort.
1. A senior physical design engineer fixes a timing issue.
2. Another engineer solves a congestion problem.
3. Someone else discovers a better macro placement strategy.
4. A team spends weeks tuning PPA across hundreds of experiments.
But most of this knowledge disappears into scripts, logs, webex threads, reports, and individual engineer's memory.
We’re changing that.
At @archgen_ , we’re building self-learning agents for semiconductor design, with specific focus on physical design.
Our agents work alongside engineers, run EDA flows, inspect reports, debug failures, optimize PPA, and capture the reasoning behind successful workflows.
1. When an engineer solves something, the agent learns.
2. When a strategy fails, the agent remembers why.
3. When a similar problem appears again, the agent can reuse the right approach.
Over time, this becomes an organisational memory layer for chip design. One that compounds.
Our vision is to make chip design feel less like manually stitching together fragmented tools and more like working with a team of expert agents that get better every day.
The future of semiconductor design is self-learning.
Huge thanks to @suhasasumukh 🐐 and @localhosthq for being extremely generous with their credits and supporting us throughout.
#semiconductors #EDA #physicaldesign #ASIC #chipdesign #AI
Weekend update :
@HariAyapps and I contributed to OpenROAD today:
https://t.co/R2w76gh38t
OpenROAD is one of the most widely used open-source digital physical design toolchains, with ~3K GitHub stars and growing adoption across research and industry.
We’ve been heavily using OpenROAD as part of the @archgen_ stack for our physical design workflows, so it feels good to finally contribute something back upstream.
Open-source EDA infra is genuinely catching up to the big players.
Seeing some really powerful results from GPT 5.4 as a macro placement engine opposed gemini, AlphaChip and autoDMP.
Best timing for RISC-V processors so far and some improvement in power consumption as well
Launching something we’ve been working for a while - AI agents to build chips faster.
Applied to YC. Let’s see where this goes 🚀
https://t.co/95tXXXh5IU
I explored subagent mode in claude code . It is really dope.
Each agent will get a dedicated system prompt and specific task to do.
Using subagents i can read the CODE with one agent , and read specification implementation from doc at the same time.
Okay, I want to make the text moving in reverse Z fashion now!
I vibe coded this using antigravity - And i could complete doing it in 2 hours. That was really nice!!
Next : Can i display live stock data using @zerodha API? One way to find out!!
Stay tuned.
ChatGPT somehow guessed I’m in Tirupati after just two questions about my relative’s aero-college hunt. How?! I actually live in Bangalore — I just came to Tirupati for a vacation.
Cooked this with my buddy @HariAyapps over the weekend 🍳
After a 3 AM duel with HDL, the FPGA finally said it — “nexusResearch is Online…” Wi-Fi → FPGA → LCD ✅
AI helped debug (after testing my patience 😅)
Imagine this:Instead of manually logging every coffee, train ticket, or impulse online buy ,chill. This expense tracker automatically finds your bank statements, reads them like a pro, and neatly organizes everything. Sounds like sci-fi? That's exactly what I set out to build 1/2
Won best demo by people's choice at Texas Instruments AI hackathon.
Built AI agent workflow to automate RTL code generation and linting and uvm based verification. Hackathons are the best way to meet smart peeps lol. Got to work with some of the best in TI.