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The major players are perfectly capable of stacking silicon, and they use stacking in SOTA products (e.g. AMD V-Cache). However, they don't do fine-grained logic stacking - "folding" in Huawei's terminology. The reason for this isn't because the concept didn't occur to anyone; there is published research on exactly this technique going back a couple of decades. It's because moving to a smaller process node is a better option if you need more transistors. Two reasons: 1) Dissipating power from a single layer of logic is hard enough; dissipating it from a second layer through the first layer is a major problem and constrains achievable power density. 2) It's very expensive - silicon area scales directly with the number of layers, and it adds manufacturing steps and defect sources. Moving to a better process gives not just area reduction / density improvement but also better power and performance characteristics. So it's an easy choice. What is actually going on here is that Huawei doesn't have this choice available to them and is trying to spin a necessity as a virtue. For the rest of it, the industry already has a name for "optimize across device, circuit, chip and system rather than just shrinking transistors": STCO (System-Technology Co-Optimization). It is bog standard practice. Node progress is slowing down, and eventually fine-grained logic stacking will be more appealing. But right now it is a crutch.