Top Tweets for #prefetchrst2

9 months ago

Another interesting #Intel #DiamondRapids info from Linux kernel list: It seems DMR has multiple non-inclusive L3 cache, one per CBB (Core Building Block = CPU die) https://t.co/3ztn2O9m64 It fits the introduction of "read-shared" hint (#MOVRS & #PREFETCHRST2 instructions)

InstLatX64's tweet photo. Another interesting #Intel #DiamondRapids info from Linux kernel list: It seems DMR has multiple non-inclusive L3 cache, one per CBB (Core Building Block = CPU die)
https://t.co/3ztn2O9m64
It fits the introduction of "read-shared" hint (#MOVRS & #PREFETCHRST2 instructions) https://t.co/Jj6dPMc0DJ

InstLatX64 @InstLatX64

9 months ago

Actually, this die configuration is not new information, it was already mentioned on this removed slide: (Although the CPU die's CBB name is seems still new.)

InstLatX64's tweet photo. Actually, this die configuration is not new information, it was already mentioned on this removed slide: (Although the CPU die's CBB name is seems still new.) https://t.co/558acQhTlZ

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