Amateur ASIC/FPGA designer building gaming hardware & GPUs. Write a 3D rasterizer on an MCU. Retro PC enthusiast. Teaching graphics programming by day.
TinyGPU v3.0 is coming with a programmable Pixel Shader!!
Tested on FPGA and submitted to the #TinyTapeout May shuttle (~290k transistors).
This Chameleon demo is a tribute to the #GeForce 3, the first programmable GPU released 25 years ago. https://t.co/GCy7tmGfUA
@BreakingTaps@r0b0t_sp1der Oh so your chip is not RISCV. Wow building a compiler would be a hugh task. It is so cool that you can build the whole tech stack. 👍
@BreakingTaps@r0b0t_sp1der Have you also done taped out via TinyTapeout? Is the Physical design of the whole chip more involved than that of the TinyTapeout?
@Ryuz88 Agree. For the individual ASIC fab, I think it is about 40 years ago, ex. i386 CPU. I also agree that making alternate version of the chip, "things that could have been done", is much more fun than trying to do hardware emulator of the old chip.
@MartinPiper@ModernVintageG Thanks. Do you have a ref/link to the buffer visualization of Sega X board. I mean I would like to know in term of the game design. How many rotation/scaling image for each sprite. Or how they arrange those sprite on the screen space.
@Kuratius Yeah, I have no plan of writing an Assembler for my shader. Writing an assembler is not too hard actually, but it is super not fun to write.
For this super small shader, writing in hex also gives you the ASMR, minimal zen like feeling.
@SebAaltonen Thanks. Early-z and hierarchical-z are really cool. For this TinyTapeout GPU, my biggest hurdles are the suffocatingly narrow memory bandwidth and the tiny amount of on-chip cache.
Every pixel needs a depth test, but RAM is slow.
TinyGPU v3.0 hides that latency by running shader execution in parallel with Z-buffer access.
That jump—from a fixed pipeline in v2.0 to a 31-instruction pixel shader core in v3.0—happens without dropping a single frame 🚀