SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute. With SiFive, RISC-V has no limits!

[SiFive @SiFive]

Josh Smith, Senior Principal Engineer at SiFive, reveals how SiFive are able to deliver balanced performance CPU core IP into the area and power-conscious consumer and commercial market segments through unique microarchitectural innovation

Click the video to watch now: https://t.co/XD5NgjnEEP

#sifive #CPU #RISC-V #RVA23 #EdgeAI #AIIP #VectorProcessing #CustomAccelerators #TinyML #socdesign

[SiFive @SiFive]

Join the Futurum webinar tomorrow on May 27 at 8:00 AM PST to see how SiFive is redefining compute with out-of-order RISC-V cores that rival best in-class from legacy architectures. We’ll break down SiFive's latest performance products, the importance of compatibility with the RVA23 profile, and how to build faster, more scalable systems on a open standard.

Register here: https://t.co/9NifHETxjG

#RISCV #Semiconductors #TechWebinar #SiFive #HighPerformanceCompute #Innovation

[SiFive @SiFive]

Advancing High-Performance Computing at CTHPC 2026

The demand for high-performance, power-efficient compute architectures is growing exponentially, and RISC-V is leading the next era of innovation. As the trusted partner for RISC-V processor IP, SiFive empowers system architects and chip designers to unlock the limitless potential of custom silicon.

Are you attending CTHPC 2026 in Hsinchu? Connect with our team to discover how our advanced vector and scalar processor core IP provides the ideal foundation for next-generation AI, data center, and high-performance computing SoCs.

📅 May 28 to May 29, 2026
📍 National Yang Ming Chiao Tung University, Hsinchu, Taiwan

#RISCV #CTHPC2026 #ProcessorIP #HPC #CustomSilicon #TaiwanTech #Semiconductors

[SiFive @SiFive]

Shaping the Future of European Compute at the TSMC 2026 Europe Technology Symposium.

The RISC-V revolution is accelerating across Europe, and SiFive is leading the charge. As the trusted partner for RISC-V processor IP innovation, we are empowering system architects and chip designers to unlock limitless potential in custom silicon.

Are you looking to differentiate your next design with high-performance, power-efficient vector or scalar processing? Let���s connect in Amsterdam.

📅 May 28, 2026
📍 Hilton Amsterdam Airport Schiphol, The Netherlands

#RISCV #TSMC2026 #ProcessorIP #CustomSilicon #Innovation #EuropeTech

[SiFive @SiFive]

RISC-V is no longer just for low-power embedded tasks, it's moving into high-performance territory traditionally dominated by proprietary ISAs. Join the Futurum webinar next week on May 27 at 8:00 AM PST to see how SiFive is redefining compute with out-of-order RISC-V cores that rival best in-class from legacy architectures. We’ll break down SiFive's latest performance products, the importance of compatibility with the RVA23 profile, and how to build faster, more scalable systems on a open standard.

Register here: https://t.co/lkwczV4k5C

#RISCV #Semiconductors #TechWebinar #SiFive #HighPerformanceCompute #Innovation

[SiFive @SiFive]

The energy was electric at the TSMC 2026 Taiwan Technology Symposium, where the future of AI was on full display and our SiFive experts were on hand to showcase our latest products and connect with customers. Huge thanks to TSMC for the opportunity to join this event!

#TSMC #SiFive #RISCV #Semiconductors #AI #Innovation

[SiFive @SiFive]

SiFive is excited to be a part of the TSMC 2026 Taiwan Technology Symposium on May 14. Stop by and meet with our experts at the Sheraton Hsinchu Hotel to talk all things SiFive and explore our RISC-V solutions.

See you in Taiwan! 🇹🇼

#TSMC #SiFive #Hsinchu #TechSymposium

[SiFive @SiFive]

SiFive and HighTec EDV-Systeme are collaborating to streamline the development of safe and secure software for automotive and industrial applications. https://t.co/7IxDeSMXWX

[SiFive @SiFive]

RISC-V is no longer just for low-power embedded tasks, it's moving into high-performance territory traditionally dominated by proprietary ISAs. Join the Futurum webinar on May 27 at 8:00 AM PST to see how SiFive is redefining compute with out-of-order RISC-V cores that rival best in-class from legacy architectures. We’ll break down SiFive's latest performance products, the importance of compatibility with the RVA23 profile, and how to build faster, more scalable systems on a open standard.

Register here: https://t.co/azFvRNBuY6

#RISCV #Semiconductors #TechWebinar #SiFive #HighPerformanceCompute #Innovation

[SiFive @SiFive]

Inside SiFive | Episode 1: RISC-V and the Automotive Market

The automotive industry is at a turning point. As ADAS and zonal designs redefine the vehicle, the shift toward the RISC-V open standard architecture is accelerating.

Join us for the first episode of the “Inside SiFive” podcast series. In this wide ranging and informative conversation, SiFive experts share key insights about the state of RISC-V within the automotive industry and how SiFive is in the driver's seat to meet customer needs for the next generation of vehicles.

Watch the pilot episode here: https://t.co/uj0suyShkT

Learn how SiFive™ Automotive solutions provide the flexibility and performance required for the road ahead: https://t.co/IgoF1xC7Gi

#RISCV #SiFive #AutomotiveTech #ADAS #ZonalArchitecture #ProcessorIP #OpenStandard

[SiFive @SiFive]

May the 4th Gen be with you!

The SiFive Essential™ 4th Gen processor IP is the ideal solution for a vast galaxy of embedded and real-time control applications. Whether you are designing for droids, speeders, or in-cockpit instrument clusters running RTOS or rich Linux environments, this is the IP you are looking for…

Throw that legacy ISA into the trash compactor and join us in the RISC-V revolution. Discover how open standard designs can accelerate your next mission. Contact us to learn how!

#SiFive #MayTheFourthBeWithYou #Semiconductors #TechTransformation #RISCV #StarWarsDay #EmbeddedSystems

[SiFive @SiFive]

Catch us at Booth #520 at the TSMC 2026 Technology Symposium.

Stop by right now to chat with our experts and see our latest architectures in action. Learn how our latest RISC-V architectures accelerate performance for AI applications from Embedded Edge to the Data Center. Discover why SiFive is the RISC-V gold standard.

#SiFive #TSMC2026 #RISCV #Semiconductors #AI #Innovation #Compute #SantaClara

[SiFive @SiFive]

Join SiFive at the TSMC 2026 North America Technology Symposium to see how we are reshaping the global compute landscape. As the trusted partner for RISC-V IP innovation, we are leading the revolution by empowering chip designers with high-performance and power-efficient processor IP.

Stop by Booth #520 at the Santa Clara Convention Center on April 22nd to learn how our latest RISC-V architectures accelerate performance for AI applications from Embedded Edge to the Data Center. Discover why SiFive is the RISC-V gold standard.

Date: April 22, 2026
Location: Santa Clara Convention Center, Santa Clara, CA
Booth: #520

#RISCV #DataCenter #AI #SiFive #TSMC2026 #Semiconductors #TSMC

[SiFive @SiFive]

Thank you @Nasdaq for celebrating SiFive's funding milestone. Exciting to see our logo in #TimeSquare. Maybe one day we will be there to ring the bell! 

#SiFive #RISCVMomentum #IPOBound #Nasdaq #RISCV #AgenticAI

[SiFive @SiFive]

It was cool to see our logo inside the exchange. Thank you @NYSE for the recognition of our latest funding milestone and for giving Wall Street a preview at what could be down the road…

#SiFive #RISCVMomentum #IPOBound #NYSE #RISCV #AgenticAI

[SiFive @SiFive]

BIG NEWS: SiFive has successfully closed an oversubscribed Series G financing round of $400 Million, bringing our valuation to $3.65 Billion.

Led by Atreides Management, with participation from A-list investors including NVIDIA, this investment is a major vote of confidence, with funds targeted specifically to accelerate SiFive’s high-performance RISC-V data center solutions roadmap to service the outsized demand for Agentic CPUs within the hyperscalers.

As CEO Patrick Little notes, "As the industry evolves toward agentic AI, SiFive is doubling down on the data center. Through collaborations with our customers we are uniquely positioned to capture a meaningful portion of the massive agentic AI shift."

We are excited to continue pioneering, and to be leading the RISC-V revolution into the next era.

Read the Press Release: https://t.co/hQPRWh8yfP

Read the Blog: https://t.co/qRvyGMaxNI

#RISCV #AgenticAI #DataCenter #VentureCapital #Semiconductors #SiFive #AIInfrastructure

[SiFive @SiFive]

Join us for a free, 60-minute live webinar to explore why RISC-V IP is moving rapidly into the practical implementation phase.

As a leading RISC-V IP vendor, SiFive will be diving into the technical trends and real-world applications shaping the industry today.

Title: SiFive – Latest Trends in RISC-V IP: Entering the Practical Implementation Phase
Date: April 21, 2026
Time: 10:00 – 11:00 (JST) → SiFive Featured Session (10:00 - 10:30)
Cost: Free

We’ll be introducing our latest product portfolio and discussing the shift from "Concept" to "Practical Use" at the forefront of RISC-V technology. Whether you are an architect, engineer, or tech leader, this is a deep dive you won't want to miss.

👉 Register here to secure your spot: https://t.co/RZDIyeNDXs

#SiFive #RISCV #Semiconductors #Webinar #TechTrends #Innovation #JapanTech

[SiFive @SiFive]

Why wait for silicon? 🛡️

@Synopsys collaborates with SiFive to deliver Synopsys VDKs for our diverse range of automotive certified processors. By providing cycle-accurate models within the Synopsys Electronics Digital Twin Platform, we’re helping engineers conquer the complexities of new zonal architectures with real-time precision.

Check out how we’re accelerating the future of mobility.
https://t.co/rJnC5Va7ov

#AutomotiveDesign #DigitalTwin #EmbeddedSystems #SiFive

[SiFive @SiFive]

Why the "Zonal Shift" Demands a New Approach for Automotive Compute

The modern vehicle is no longer just mechanical; it’s a highly complex electronic system of sensors, wiring and compute. In many cases car manufacturers are having to completely re-engineer their cars from the ground up.  As part of this, automotive architectures are evolving to Zonal controllers to reduce cost, weight, and power.

Strict real-time performance, functional safety, and cybersecurity are no longer "nice-to-haves"—they are the baseline.

At SiFive, we believe RISC-V is the key to unlocking this next generation of automotive. By leveraging an open-standard ISA, we aren't just improving performance; we are:
✅ Boosting supply chain resilience.
✅ Bringing standards-based RISC-V ISA for safety and compute
✅ Providing customers with a roadmap backed with years of investment

The future of automotive is open, with freedom from single-vendor lock in.

Discover how SiFive is powering the Zonal revolution: https://t.co/8qzuYh8tl0

#AutomotiveDesign #RISCV #ZonalArchitecture #Semiconductors #SiFive #FutureOfMobility

[SiFive @SiFive]

Ever wondered how RISC-V stays so efficient while keeping hardware simple? It all comes down to how we handle addressing modes in software rather than hardware.

In our latest technical blog, we explore the vital role of Code Models within the RISC-V toolchain and how they empower designers to optimize performance.

Key Takeaways:
▪️Simplicity by Design: RISC-V minimizes hardware costs by using only three basic addressing modes: PC-relative, Register-offset, and Absolute.
▪️Software Flexibility: We rely on modern toolchains to optimize addressing, achieving similar code size to complex ISAs with vastly simpler decoding rules.
▪️Medlow vs. Medany: Learn the functional differences between these two primary code models and how they determine where your code can be linked in the address space.
▪️ABI vs. Code Model: We clear up common misconceptions about how code models interact with function interfaces and pointers.

By using fusible multi-instruction sequences and linker relaxation, RISC-V offers the power of variable-length addressing without the hardware bloat.

Read the full technical breakdown here: https://t.co/m2jEZqukCJ

#SiFive #RISCV #Semiconductors #ComputerArchitecture #Coding #TechBlog #OpenStandard