Taτsu

Taτsu is a decentralized AI crypto project focused on developing on the Bittensor network. Taτsu Validator

[Taτsu @TatsuEcosystem]

The TatsuOS Whitepaper and six-month roadmap are live.

TatsuOS is a new utility for the TATSU token — and a new answer to a problem the IoT industry has never properly solved: when you buy a connected device, the vendor owns its features, not you.

TatsuOS changes that. Burn $TATSU, unlock a feature, own it forever — no subscription, no phone-home dependency, no vendor that can revoke it. The receipt is cryptographically signed and verified on the device itself.

But the receipt mechanic is just the foundation. On top of it: a managed telemetry pipeline, fleet-wide dashboard, over-the-air firmware and model updates, on-platform AI model training, and AI agents that help you build models from your own device data — without standing up your own MLOps stack.

One platform. One token. No separate vendors.

The six-month roadmap:

Month 1 — Hardening and Ethereum testnet deployment.
Full burn → BLE → unlock flow on real ESP32 hardware. Production signing key in KMS. Contracts fuzz-tested and frozen.

Month 2 — Closed pilot.
Ten devices in five community members' hands. Real burns, real unlocks. Target: ≥90% receipt delivery success on first attempt.

Month 3 — Multi-board support.
Firmware runs on nRF52 and STM32 alongside ESP32. Telemetry SDK published as a standalone Zephyr module with templates for agriculture, industrial, and consumer use cases.

Month 4 — Public beta.
JS/TS SDK on npm. Self-service dashboard and docs go live — from clone to first unlock in under 30 minutes.

Month 5 — Audits.
Two independent third-party audits (contracts + firmware), full reports published, all critical findings remediated. Mainnet dry-runs complete.

Month 6 — Ethereum mainnet launch.
Contracts live under multi-sig. Firmware and SDK 1.0 released. First commercial OEM ships TatsuOS-enabled devices. First quarterly state-of-TatsuOS report: total devices, total unlocks, total TATSU burned.

Read the full white paper: [https://t.co/mJt6j9krdu]

[Taτsu @TatsuEcosystem]

TatsuOS Update: Fleet Dashboard 🚀

We just build the first version of the TatsuOS Fleet Dashboard for inhouse testing — and it's coming together exactly as we envisioned.

We simulated multiple devices, generated real telemetry data, and built a dashboard that turns raw hardware signals into something an operator can actually use to manage a fleet. We're still in active development and not open to users yet — but we're building this the right way, and it won't be long before it is.
Here's what it does:

🖥️ Fleet Overview — Every device as a card. Board, firmware, online/offline, last-seen, telemetry counts, unlock history. Everything at a glance.
📈 Live Telemetry Charts — Every sensor plotted over time. Merged view or split per-sensor, each showing min, max, and current values. Your hardware, visualized.
🔓 Feature Unlock History — Every burn-to-unlock logged per device with nonce and transaction hash. Full on-chain traceability.
📤 Export — Pull any device's telemetry as CSV, JSON, or Parquet across any time range. Your data, your format.
⚡ Auto Offline Detection — Device goes quiet for 2 minutes? It flips offline automatically.

This is a first draft — the designs will keep improving as we move through the UI pass. But the foundation is there, and it works.
More coming soon. 👀
ScreenShots ⬇️

[Taτsu @TatsuEcosystem]

Sunday Brief – June 21, 2026

TatsuOS Development Update: Fleet Dashboard
- Simulated multiple devices to generate real telemetry data, then built a dashboard to turn that data into something operators can actually use
- Fleet overview: every device shown as a card with name, board, firmware version, online/offline status, last-seen timestamp, and telemetry/unlock counts
- Per-device telemetry charts: every sensor plotted over time, viewable as one merged graph or split per-sensor with min/max/current values
- Feature-unlock history: full burn-to-unlock log per device, including nonce and transaction hash
- Export functionality: pull device telemetry as CSV, JSON, or Parquet for any selected time range
- Devices offline for more than two minutes automatically flip to offline status
- These are first-draft designs, refinement to follow as part of the broader UI pass

Chip Design Team
- RVGEN continues to mature as the foundation of our instruction-level verification flow and future challenge infrastructure
- Built and tested the first version of a high-level validation pipeline aimed at evaluating hardware through real applications rather than individual instructions
- Tested it using the ChipForge MCU (built through miner contributions), running a real image-classification neural network on both the baseline MCU and the floating-point-enabled version — results matched expectations, with hardware FP showing a significant performance edge over software-emulated FP
- Since future challenges will focus on accelerators, we integrated a simple matrix accelerator into the flow — it delivered roughly an 8× performance improvement, validating the overall approach and surfacing areas for refinement
- The goal wasn't the accelerator itself, but proving the pipeline can fairly and correctly evaluate future miner-submitted accelerator designs through real workloads, not just low-level instruction tests
- First version is working, but more testing and refinement are needed before it's production-ready for when ChipForge returns

[Taτsu @TatsuEcosystem]

🚀 TatsuOS Development Update: Token Spend Portal Testing Complete
We just finished full testing of the Token Spend Portal on a local chain.
Used three different tools because they catch different kinds of bugs:
✅ Hardhat — 17 example tests covering registration, feature updates, ownership transfer, and the full approve → spend flow. All green.
✅ Foundry — 8 Solidity tests + fuzz testing with 256 randomized inputs. Confirmed exact-cost accounting — every spend reduces balance and total supply by precisely the feature price. No leaks.
✅ Echidna — Ran 50,141 random transaction sequences. Verified 4 invariants after every single transaction:
- Supply never increases
- Nonce always matches spends
- Nonce never rewinds
- Books always balance
Result: Everything passed cleanly.
Frontend: Basic Spend Portal is already working end-to-end (wallet connect, feature grid, two-step flow with Etherscan links). Solid baseline ready.

[Taτsu @TatsuEcosystem]

Sunday Brief – June 14, 2026
A great chip is only useful when software can take full advantage of it. That's why, alongside verification and hardware development, we continue investing in the compiler and software infrastructure that future AI accelerators will depend on.
This week, work continued on building the software foundations needed for future matrix-engine and AI-accelerator development, while verification tooling also received improvements aimed at covering harder-to-reach corner cases.

Chip Design Team
- Continued work on the compiler and software stack required for future AI accelerator development, with focus on building an end-to-end environment that can support future matrix-engine integration
- Added a new directed instruction stream to RVGEN targeting RISC-V memory-ordering verification, covering fence-ordering scenarios that default random generation could not reliably reach
- Verified the new flow end-to-end using real GCC-generated assembly
- Improved the `--help_streams` interface to expose stream conflicts and CSR side effects directly from the terminal, making generator behavior easier to understand and control
- Further work remains on both the compiler infrastructure and verification tooling as we continue building the foundations needed for future MCU and AI-accelerator development
Building hardware, verification infrastructure, and software together remains the long-term goal. Each piece strengthens the others, helping ensure future systems are both powerful and usable from day one.

Tatsu Ecosystem Website
- New website tested, finalized, and officially launched — live for everyone to explore

TatsuOS Development Update: Token Spend Portal Testing
- Tested the spend contract across three layers on a local chain — Hardhat (17 example tests covering core flows), Foundry (8 tests including a 256-input fuzz test verifying exact-cost accounting with zero drift or leaks), and Echidna (50,141 randomized transaction sequences checking key invariants like supply, nonce, and balance integrity)
- All tests pass — no sequence of calls could push the contract into a bad state
- Frontend Spend Portal working end-to-end — wallet connection, hashed device ID, feature grid, and two-step transaction flow with Etherscan links. This is the working baseline; UI polish to follow.

[Taτsu @TatsuEcosystem]

The new Taτsu website is officially LIVE.
We rebuilt it from the ground up—it's cleaner, sharper, modern, and finally represents the true scope of what we're building.
We’re skipping the long speech about technical details and the grind behind the scenes. Just hit the link and check it out yourselves:
🔗 https://t.co/zIF0WWVe8F
Let us know what you think!

[Taτsu @TatsuEcosystem]

Tatsu Ecosystem new website drops tomorrow.
We rebuilt it from the ground up — cleaner, sharper, and actually representative of what we're building. Here's a sneak peek at what's coming.
Stay tuned.

[Taτsu @TatsuEcosystem]

Sunday Brief – June 7, 2026

Verification helps build reliable silicon. But without the right compiler and software ecosystem around it, even great hardware struggles to reach its full potential.

That's why our focus is expanding beyond verification alone. Alongside building stronger hardware validation infrastructure, we're also starting to invest in the software foundations that future accelerators will depend on.

This week marked the completion of a two-week effort to strengthen RVGEN's foundations, while also expanding work into the compiler and software ecosystem needed for future AI accelerator development. The goal is simple: ensure that hardware and software evolve together, eliminating bottlenecks before they appear.

Chip Design Team

- Resolved the remaining 5 medium-severity findings from last week's review, bringing the total to 12 of 12 identified issues fixed, with every fix protected by regression tests.
- Added 11 new tests, increasing RVGEN to 1,050 passing unit tests while maintaining a clean validation baseline and further strengthening coverage accuracy, reproducibility, and user-controlled generation flows.
- Continued work on improving challenge generation performance and scalability, supporting future validator-driven runtime test generation and broader verification coverage.
- Started development of the compiler infrastructure required for AI workloads, establishing an end-to-end software environment that can run models on today's FPGA-based platforms while preparing for future accelerator integration.
- Early work is focused on ensuring that future matrix-engine and accelerator developments can be accompanied by a mature software stack from day one, enabling hardware and software co-development rather than sequential development.

The result is a stronger verification foundation today and a clearer path toward the next generation of AI-focused hardware and software infrastructure.

Tatsu Ecosystem Website
- Complete revamp — rebuilt from the ground up to feel dynamic, lively, and reflective of what we're actually building with TatsuOS
- Final touch-ups underway, testing across multiple display sizes and load conditions
- Going live in upcoming week — we'll let the work speak for itself

[Taτsu @TatsuEcosystem]

Sunday Brief – May 31, 2026
Sometimes the fastest way forward is to stop adding new things and take a hard look at what already exists.

That was the focus this week. Rather than expanding RVGEN with new features, the team turned its attention toward the correctness of the generator itself. The goal was simple: make sure RVGEN generates the right test cases across the many different ways a verification engineer might use it — different processor configurations, instruction streams, generation constraints, coverage settings, and user-controlled flags. As expected, the tests uncovered a number of issues in scenarios that were not behaving exactly as intended. In total, 12 issues were identified, including 7 high-severity findings. All seven were fixed during the same cycle and protected with new regression tests.

Chip Design Team
- Added 39 new tests this week, bringing RVGEN to 1,039 passing unit tests while maintaining a clean Spike validation baseline
- Extensive testing across different generator configurations, instruction streams, and user settings uncovered 12 issues, including 7 high-severity and 5 medium-severity findings
- All 7 high-severity issues were fixed during the same cycle and protected with new regression tests
- The remaining medium-severity issues have already been identified and will be addressed in upcoming updates
- The fixes improved coverage accuracy, seed reproducibility, and enforcement of user-defined generation controls across all supported generation flows
- Internal testing continues to show strong generation performance, while broader benchmarking against other instruction generators remains ongoing
- Work also continued on the agent-based verification pipeline discussed in previous briefs
- The long-term goal remains the same: make it easier and faster to validate miner-submitted bugs and fixes, helping verification scale across both the MCU and NPU roadmap

Before relying on a verification tool to find bugs in a processor, it's worth making sure the tool itself behaves correctly. That was the focus this week, and the result is a stronger RVGEN foundation for everything that will be built on top of it.

TatsuOS
Tatsu Ecosystem Website
- Studied a design reference and adapted its visual language — recreated the depth, shadow, and motion styling for the website.
- Streamlined the site — removed dead sections and data fetches, making the homepage lighter and faster.
- Built custom graphics — a self-contained, library-free canvas engine powering the interactive network visuals.
- Rebuilt key layouts — refined section structure and fixed sizing so visuals fill their space cleanly.
- Rebranded around the real logo — recolored it to match the theme, set the proper wordmark, and cleaned up the site's identity throughout.
- Engineered animations for the website to make it look lively instead of stagnant and bland.

[Taτsu @TatsuEcosystem]

Sunday Brief – May 24, 2026
TatsuOS reached a major milestone this week with the smart-contract API frozen, core interfaces locked, CI and change-control finalized, and fuzz testing planned next.

At ChipForge, verification is one of the most important parts of the entire chip design flow. Miners finding bugs, fixing bugs, stress testing designs, and validators checking whether those bugs and fixes are actually real, that is what makes decentralized chip design possible in practice. A major part of the current effort is going into making that flow faster and more scalable. RVGEN continues improving the test-generation side of verification, while the agent-based validation pipeline is being developed to reduce manual effort in validating miner-submitted bugs and fixes. Together, both systems are aimed at significantly reducing development iteration time across the MCU and NPU roadmap.

Chip Design Team

- Work on RVGEN continued this week, with focus on improving both usability and deeper verification coverage
- Added directed cache-conflict generation support, allowing the generator to intentionally create memory access patterns that collide on the same cache sets and stress cache eviction and replacement behavior during verification
- The generator now includes explicit cache-conflict coverage tracking, further extending the overall verification coverage infrastructure
- Improved the command-line workflow, making it easier for verification engineers to quickly explore available tests, streams, and targets directly from the terminal without depending heavily on documentation
- RVGEN now passes over 1000 unit tests while maintaining full Spike validation across the internal regression plan
- Internal testing also shows very strong generation performance, currently running more than 10x faster than some SystemVerilog-based generation flows in comparable scenarios, though broader benchmarking against other widely used generators is still ongoing
- Work also continued around the agent-based verification pipeline discussed earlier, particularly around how it can be adapted cleanly for larger CoralNPU verification flows
- The long-term goal is to automate larger parts of bug triage and challenge validation, where miner-submitted tests and fixes can be analyzed, classified, and validated much faster with minimal manual effort, while still keeping the overall flow reliable and scalable

TatsuOS
- The smart-contract API is now frozen as the first major milestone
- The TatsuBurn contract interface, events, and receipt format are now locked to provide a stable target for firmware, signer infrastructure, SDK integration, and future auditing
- Completed full Hardhat-based test coverage for burn flow, feature registration, access control, and edge cases
- CI validation now runs automatically on every pull request before changes can be merged
- Dependency versions were pinned and stricter change-control rules were introduced around contract modifications
- Next phase will focus on property-based fuzz testing using Foundry and Echidna to stress deeper contract invariants and randomized transaction flows

Both the verification infrastructure and TatsuOS roadmap continue moving toward the same goal: building reliable systems that can scale without sacrificing correctness.

[Taτsu @TatsuEcosystem]

TatsuOS Development Update — The Smart-Contract API Is Frozen

This week marks the first milestone of the TatsuOS six-month roadmap: the smart-contract API is now frozen. The TatsuBurn contract — its functions, its events, and the receipt format it produces — will not change again before a Team decision.

Freezing the contract API is a deliberate engineering decision. The contract sits at the centre of the platform: the firmware, the cloud signer, the burn portal, and the developer SDK all depend on its interface. Allowing that interface to keep shifting would force continuous rework across every component — and would make a meaningful audit impossible, since an audit reviews one specific version of the code. By locking the interface now, every later workstream can build against a stable target.

Completed this week:
- Test coverage. The TatsuBurn contract is covered by a full Hardhat test suite, exercising the burn flow, feature registration, access control, and edge cases.
- Continuous integration. That suite now runs automatically on every pull request. No change is merged without a passing run.
- Locked dependencies. Dependency versions are pinned so that no silent upstream update can alter behaviour unexpectedly.
- Change control. Any change touching the contract or the receipt format now requires a passing CI run and a documented change note — a standard we apply to ourselves without exception.

Next: property-based fuzz testing. We will extend testing beyond fixed cases into fuzzing — using Foundry to generate thousands of randomised function inputs, and Echidna to generate entire transaction sequences that probe for any state violating a core invariant (for example, "total TATSU burned can only ever increase"). Fuzzing tests the cases no engineer thought to write, and a frozen API gives it a fixed target to test against.

This is the first week on the roadmap, and one of the most important. A frozen, well-tested foundation is what allows every subsequent milestone
— the KMS-backed signer, the on-device firmware verifier, and the third-party audit — to proceed with confidence.

[Taτsu @TatsuEcosystem]

@JohnKemsa33577 Not yet

[Taτsu @TatsuEcosystem]

Sunday Brief – May 17, 2026
A delivery and foundation week. RVGEN officially launched as an open-source instruction generator, and the TatsuOS whitepaper was released with a detailed six-month roadmap.

Brief Summary
This week we moved from preparation to public release. RVGEN, the ChipForge instruction generator mentioned last week, is now live and available via pip. It's already surfacing real compliance bugs in external usage and strengthening our internal verification flows. In parallel, the team completed an initial end-to-end test of an agent-based verification pipeline designed to automate bug validation and challenge evaluation. On the TatsuOS side, the whitepaper dropped with a comprehensive technical breakdown and a tentative six-month roadmap. Both projects are accelerating toward faster execution.

Chip Design Team
- RVGEN officially launched under the Tatsu Github organization: `pip install rvgen`
- Source code available at https://t.co/lbToKKPD6s
- Modern chip verification depends on generating massive amounts of meaningful randomized programs while controlling corner cases, privilege transitions, vector behavior, traps, and mixed workloads — RVGEN was built to solve that problem
- Supports 29 built-in RV32 and RV64 targets covering scalar integer, floating-point, vector, compressed, cryptography, hypervisor, and newer RISC-V extensions
- Designed to be self-contained and easier to extend compared to existing flows, removing the need for large external riscv-dv setups
- Currently passes 989 unit tests and 213/213 Spike validation cases across the internal verification plan
- Already in use internally on both CoralNPU and ChipForge MCU; external adoption this week surfaced multiple real compliance bugs that have since been fixed
- Completed initial end-to-end test of agent-based verification pipeline to automate bug validation and challenge evaluation at scale
- Both RVGEN and the agentic validation flow are being built to support a much faster challenge cadence once the subnet returns

TatsuOS
- Released whitepaper outlining the full technical architecture and vision for the project
- Worked through technical details and complexities with the team, producing a comprehensive yet tentative six-month roadmap
- Moving forward, we'll be posting TatsuOS progress updates twice a week to keep the community informed as development accelerates

[Taτsu @TatsuEcosystem]

Sunday Brief – May 10, 2026
A rebuilding and preparation week. Following last week's subnet deregistration, the team has shifted focus to strengthening the foundation — accelerating challenge creation infrastructure and advancing TatsuOS development.

Brief Summary
With ChipForge temporarily offline, we're using this time to remove bottlenecks and build faster. The chip design team is preparing the next challenge set while open-sourcing the ChipForge instruction generator — a tool that will dramatically speed up test generation and verification. In parallel, work continues on agent-based validation and TatsuOS development. We're building steadily toward re-registration with stronger infrastructure and clearer execution.

Chip Design Team
- Preparing next challenge set to launch once the subnet is re-registered
- Identified a major bottleneck: large-scale test generation and verification infrastructure for complex RISC-V workloads
- Developed ChipForge instruction generator to solve this — will be open-sourced before next Sunday
- Supports randomized instruction generation across scalar integer, floating-point, vector, privileged, and unprivileged modes for both RV32 and RV64
- Already in use internally for regression and stress testing on both CoralNPU and ChipForge MCU
- Continuing work on **agent-based validation pipeline** to automate larger portions of verification and challenge validation flow
- Goal: launch challenges at a much faster rate and accelerate development across NPU and MCU tracks

TatsuOS Development
We're also building TatsuOS — an IoT fleet management platform powered by $TATSU token economics.
Think: real hardware, real burns, real unlocks. Ethereum-based smart contracts managing embedded devices running trained AI models, with over-the-air updates and multi-MCU support.

Full roadmap and whitepaper dropping next Week. Stay tuned.

[Taτsu @TatsuEcosystem]

An Update on the Taτsu Ecosystem: The Path Forward

Our Subnet ChipForge has been deregistered. While our technology remains excellent—recently proven by our open contributions to Google's Coral NPU— we still were caught in the cycle of deregistration process.
​High-end chip design is a sophisticated, capital-intensive field that demands advanced engineering and patience, but it offers unparalleled revenue potential in the long run. We are not slowing down; instead, we are refining our focus into two parallel tracks that leverage the full spectrum of our team’s capabilities.

Track 1: ChipForge — Our Main Focus
ChipForge remains our elite hardware design arm. Our work solving complex chip-design challenges through open competition is a core part of our identity. We will maintain ChipForge as our main focus, preparing for a return to the Bittensor ecosystem when the registration and economic environment align with our long-term hardware roadmap.

Track 2: TatsuOS — The Commercial Product
In parallel, we are accelerating TatsuOS, our AI-native IoT platform. While ChipForge pushes the boundaries of future hardware, TatsuOS solves the practical, commercial challenges of the IoT industry today—ending the "subscription trap" and vendor lock-in.

• Commercial Utility: TatsuOS enables "Burn-to-Unlock" features using the $TATSU token, granting users permanent, cryptographic ownership of their device features.
• Infrastructure Simplified: Managed telemetry pipelines, fleet-wide dashboards, and over-the-air (OTA) updates are standard, replacing three separate vendor contracts with one unified platform.
• The AI Agentic Pipeline: This is the heart of TatsuOS. We are democratizing Edge AI. Our platform allows anyone to turn an idea into a deployed model via Agentic pipelines. You no longer need a team of Data Engineers, AI researchers, or MLOps specialists.
◦ Example: "I want my soil sensor to detect water stress 24 hours earlier"—our AI agents handle the data engineering, model training, and deployment directly to your devices over the air.
• A New Home for $TATSU: This creates a direct, undeniable link between the token and real-world product usage across thousands of devices.

We are building both in parallel—one to design the chips of the future, and one to power the devices of today. We will continue to provide weekly, data-driven updates on both fronts.
The technology is solid. The strategy is clear. Let's hope for the best.
— The Taτsu Team

[Taτsu @TatsuEcosystem]

Sunday Brief – May 3, 2026
Learning, Adjusting, and Moving Forward

Brief Summary
Our Subnet ChipForge has been deregistered from Bittensor. That’s where things stand this week. Not the result we were aiming for.
But nothing has stopped on our side. The team is still working and the direction hasn’t changed. What this changes is how we approach things going forward.
Building chips is not a short game. It takes time to reach a product, and even more clarity to explain its value properly. We’re taking this moment to tighten both how we build and how we present what we’re building.

What’s Next
- Chip design work continues, both on the NPU side and the MCU pipeline
- The validation and infrastructure systems are still being improved and refined
- We are rethinking how we position this work, so the scale and importance of what’s being built is understood clearly
- Working toward a more sustainable path alongside long-cycle hardware development

We’ve already built real systems, real silicon flows, and real progress over the past months. That doesn’t disappear because of one deregistration.

We’ll come back better prepared, with a clearer plan and stronger footing.

And we’ll keep building.

[Taτsu @TatsuEcosystem]

Our Subnet ChipForge (SN84) has been deregistered from Bittensor.

Not the outcome we wanted, but we're not stopping. We're regrouping, planning smarter, and coming back stronger.

The vision remains: decentralized chip design that works. We'll keep building toward it.

Thanks to everyone who believed in what we're doing. More soon.

[Taτsu @TatsuEcosystem]

We launched Challenge 0014, focused on completing the RV32F (floating-point) extension for the ChipForge MCU. This means our processor can now handle real (decimal) numbers along with whole numbers, enabling more advanced calculations.

Miners are adding support for floating-point operations such as division (FDIV) and square root (FSQRT), along with more advanced combined operations (FMADD/FMSUB/FNMADD/FNMSUB) and comparisons (FEQ/FLT/FLE). They are also enabling the processor to identify different types of numbers (FCLASS) and handle decimal data in memory using FLW/FSW, including more compact (compressed) versions.

All designs must match Spike (the golden reference model for RISC-V) exactly, ensuring our processor behaves identically to the standard reference, and must follow IEEE 754 rules for accurate and consistent real-number calculations.

Support is also being added for control registers like fflags, frm, and fcsr, which control rounding and exception behavior. For example, a result like 3.5 can become 4 (round up) or 3 (round down) depending on the selected rounding mode.

Extensive testing is conducted to ensure stability and correctness of the challenge.

Additionally, we have introduced stronger checks in the evaluation system to make it much harder for miners to game the system, ensuring fair and reliable results.

[Taτsu @TatsuEcosystem]

Sunday Brief – April 27, 2026
Challenge 0014 is now live, completing full RV32F floating-point support for the ChipForge MCU, with significant infrastructure improvements deployed across the platform.

Brief Summary
Building on Challenge 0013's floating-point foundation, we've launched Challenge 0014 to implement the remaining RV32F instructions—including division, square root, fused multiply-add, comparisons, load/store, and full CSR support. This completes the single-precision floating-point extension for our IoT MCU. In parallel, the challenge server received major upgrades to improve transparency, performance tracking, and submission lifecycle management. All services underwent extensive testing to ensure stability and reliability.

Chip Design Team
- Challenge 0014 launched, targeting full RV32F extension completion for ChipForge MCU
- Miners now implementing: FDIV, FSQRT, fused MAC (FMADD/FMSUB/FNMADD/FNMSUB), comparisons (FEQ/FLT/FLE), FCLASS, FLW/FSW + compressed variants, and full fflags/frm/fcsr CSR support
- Designs must remain bit-exact with Spike and fully IEEE 754 compliant
- Extensive testing conducted to ensure challenge stability and correctness
- Additional robustness measures introduced to maintain evaluation integrity

Challenge Server
- Added EXHAUSTED status tracking to better manage submission lifecycle through rebatch cycles
- Introduced `downloaded_at` column and migration tracking for improved submission state visibility
- Leaderboard enhancements: now exposes per-validator status, evaluation timing, and submission progress counters
- Split validator performance metrics into passed-design and failed-design average times with separate counts for clearer insights
- Replaced bulky `evaluation_details` in leaderboard responses with compact preview + dedicated full-logs endpoint for better performance
- Miner info endpoint now exposes batch window sizes, allowing validators to self-configure internal timeouts dynamically
- These changes are on testnet.

Validator, EDA Server & Website
- All services tested extensively and operating smoothly
- No updates required; systems stable and ready for Challenge 0014 traffic