Hardware Architecture Papers

New Hardware Architecture papers from systems organization and hardware architecture. Thank you to arXiv for use of its open access interoperability.

[Hardware Architecture Papers @WWVY]

ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing

Ali Alipour Fereidani, Mohammad Rasoul Roshanshah, Saeed Safari
https://t.co/tyltNSheMa [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙽𝙴]

[Hardware Architecture Papers @WWVY]

SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling

Seyed Sadra Ghavami, Mohammad Hossein Nikkhah, Mohammad Rasoul Roshanshah, Saeed Safari
https://t.co/NU1KXvefFA [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙳𝙲 𝚌𝚜.𝙽𝙴]

[Hardware Architecture Papers @WWVY]

Non-Parametric Dual-Manifold Mapping via 8-Bit Bounded Transformation Matrices: Challenging FP-centric Hardware Paradigms in Low-Energy AI

Lars Kopp
https://t.co/1llacbjuBz [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics

Bochen Ye, Yihan Pan, Shady Agwa, Themis Prodromakis
https://t.co/HHdhBQbdXa [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs

Euijun Chung, Jae Hyung Ju, Hyesoon Kim
https://t.co/Anqym19oDo [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

A Fast Locality Simulator for GEMM Design-Space Exploration on Multi-Chiplet GPUs

Euijun Chung, Hyesoon Kim
https://t.co/GtL3hapLlY [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

SPEAR: A System for Post-Quantization Error-Adaptive Recovery Enabling Efficient Low-Bit LLM Serving

Hongyuan Liu, Yawei Li, Zhiqiang Que, Qinli Yang, Junming Shao, Guosheng Hu
https://t.co/xmAEl8roC1 [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙰𝙸]

[Hardware Architecture Papers @WWVY]

Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR

Elam Cohavi, Nicolas Bohm Agostini, Jude Haris, Antonino Tumeo, David Kaeli, …
https://t.co/qASyudkILJ [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙿𝙻]
💬Accepted to the 7th Compilers for Machine Learning Workshop (C4ML), co-located with CGO 2026

[Hardware Architecture Papers @WWVY]

Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA

Vinamra Sharma, Xingjian Fu, …
https://t.co/9Ms39KjX2K [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙰𝙸 𝚌𝚜.𝙿𝙵]
💬Accepted to the Machine Learning for Architecture and Systems Workshop (MLArchSys), co-located with ISCA 2026

[Hardware Architecture Papers @WWVY]

Coset Ensemble Decoder for Quantum Error Correction with Algorithm-Hardware Co-Design

Shuang Liang, Jubo Xu, …
https://t.co/O9NK9AuP7D [𝚌𝚜.𝙰𝚁 𝚚𝚞𝚊𝚗𝚝-𝚙𝚑]
💬Accepted to appear in the 53rd Annual International Symposium on Computer Architecture (ISCA 2026)

[Hardware Architecture Papers @WWVY]

Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices

Titus Bornträger, Shane Fleming, Philipp Holzinger, Dietmar Fey, Michaela Blott, Thomas B. Preußer
https://t.co/RCX2NyrO6a [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

A 185 TOPS/W/mm2 Bayesian Inference Engine with 640 aJ Write-Free FeFET GRNG for Uncertainty-Aware Aerial Search and Rescue

Zephan M. Enciso, Xuezhong Niu, Xingtian Wang, Mohammad Mehdi Sharifi, Subhasish Mukherjee, Likai Pei, …
https://t.co/IktIL9BWez [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators

Chenguang Zhang, Yuanpeng Zhang, Chenhao Xue, Yihan Yin, Chen Zhang, …
https://t.co/4vfLU53M6h [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙳𝙲]
💬Accepted by IEEE Transactions on Computers

[Hardware Architecture Papers @WWVY]

Fault Characterization and Hardening of Combinational Standard Cells Using 3D-TCAD Simulations for Cyber-Physical Systems

Ali Zarei, Amir M. Hajisadeghi, Hamid R. Zarandi
https://t.co/OJ2nRiGggx [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

A Generic Modulo-(2^n±δ) RNS Multiplier Based on Twit Representation

Saeid Gorgin, Amirhossein Sadr, Behzad Salami, Dara Rahmati
https://t.co/XSzIqSrZAZ [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques

Sheel Sindhu Manohar
https://t.co/UxU3uUa5oa [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

Sonu Kumar, Akash Sankhe, Mukul Lokhande, Santosh Kumar Vishvakarma
https://t.co/DVjvAxztaB [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙲𝚅]

[Hardware Architecture Papers @WWVY]

ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities

Marco Ho, Michael S. Hsiao, Jeeho Ryoo
https://t.co/HscZbYG64t [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙲𝚁]

[Hardware Architecture Papers @WWVY]

Toward a Small ML Runtime Stack for Raspberry Pi 5 QPUs

Yiannis Hadjiyianni, Panagiotis Michelakis, Dimitrios Stamoulis
https://t.co/0KmxDF3g2U [𝚌𝚜.𝙰𝚁]

[Hardware Architecture Papers @WWVY]

An 84-Format Numeric Catalog with Bit-Exact Conformance Vectors: A Vendor-Neutral Reference for FP8, BF16, MXFP4, and Microscaling Formats

Dmitrii Vasilev
https://t.co/VyyJDhswpD [𝚌𝚜.𝙰𝚁 𝚌𝚜.𝙰𝙸 𝚌𝚜.𝙼𝚂 𝚌𝚜.𝙿𝙵 𝚖𝚊𝚝𝚑.𝙽𝙰]
💬Code: https://t.co/WkPMQh2M6K