Congratulations to our very own Simon Robinson for receiving an Excellence in Learning and Teaching award in yesterdays graduation ceremony
Simon is one of four #ComputerScience recipients to have received a 2022 ELTA - congrats also to Shane Fleming, Neal Harman & @DrSeanWalton
Thanks so much to all the students that nominated me for this and all the colleagues who supported me over the past two long and difficult years really means a lot! And congrats to CS peeps @0x0000002a, @DelightfulApps (Simon :p) and Neal for their well deserved awards!
Welcoming a new entrant into the FPGA market: Renesas. The company just announced that they plan to make teeny, tiny FPGAs on the order of 1000-2000 gates, and sell them for less than 50 cents each in volume.
https://t.co/3D3s0g6hxP
well I just started to record a video tutorial for my module, got 15 minutes in and just couldn't do it anymore...
...at least it didn't happen in a live lecture. I can't ever remember being this tired and hearing so many colleagues say the same.
High-level synthesis for #FPGA using probabilities to model dynamic control-flow environments. A preview of @jianyi_cheng’s work he’ll be presenting at #FCCM2021 next week (joint work with @wicko3 and me)
https://t.co/kNjrk9egoi
Enjoying Marta Kwiatowska’s @bcs Lovelace Lecture. Really nice tour through the PRISM probabilistic model checker and its many applications. Tune into @jianyi_cheng ’s talk at #FCCM2021 for yet another one: optimizing dynamically-scheduled FPGA hardware!
Things are heating up in the final CSC368/M68 lab, where students have to make their TinyPico temperature sensor transmit temperature data payloads to the central server while consuming as little energy as possible.
In tomorrows lecture, I'll be live demonstrating how ping flooding a Linux based embedded system can cause substantial latency spikes. We will be comparing this to an ESP32 running a real-time operating system, where the same attack barely affects it.
I've just been appointed as a teaching lecturer at UC Santa Cruz for the spring quarter of this year. Students, get ready to learn Verilog hardware design Satnam-style!
Feeding the code into Vitis HLS is problematic for HLS tool designers like me when transforming LLVM IR back to C code, including pragmas. The new Vitis HLS front-end has significantly helped integrate our tool DASS into the HLS flow.
Our paper (me, @0x0000002a, Joy Chen, Jason Anderson, @wicko3 and @gconstantinides) "Efficient Memory Arbitration in High-Level Synthesis from Multi-threaded Code" has been accepted by IEEE Trans. on Computers. Preprint to follow.
The biggest challenge was handling some students code sending WebSocket messages as fast as the little TinyPico could. This would effectively bring the entire WiFi network grinding to a halt. It's amazing how very few (say 2 or 3) misbehaving devices can have such a big impact!
Blinking an LED is such an important part of getting started with embedded systems. Unfortunately, students in my class weren't able to physically attend, so we used the built-in WiFi of our TinyPicos to make some virtual LEDs, dance, speak, and blink.
You can also view it live here: https://t.co/5a1aZiO4iP Although the free-tier AWS server crashes sometimes and I have to get a new URL, so it may go down :P