Sandeep Kumar

Final Year ECE @ HNBGU | @TRAI Intern | VLSI & Embedded Systems Enthusiast | Creative Techie | Photographer, Singer-Songwriter & Guitarist

[Sandeep Kumar @12th_kumar]

Spent days debugging instruction decoding,Built my custom pipelined MIPS processor on Basys 3 FPGA with a working dot-product accelerator.

After endless debugging, finally got the correct hardware output: 0032.
Now I want to make it dynamic and want to cnn in it can anyone help

[Sandeep Kumar @12th_kumar]

@soucpl Semiconductors = Masters + 100 years of experience

[Sandeep Kumar @12th_kumar]

Nothing for Btech students 😭

[Sandeep Kumar @12th_kumar]

@S2SmeX Yup 👍

[Sandeep Kumar @12th_kumar]

Hello everyone, myself Er. Sandeep Kumar

Electronics and Communication Engineer

Seeking job opportunities in VLSI, Embedded Systems, FPGA Design, and Digital Electronics.

[Sandeep Kumar @12th_kumar]

@S2SmeX @goli_betaa @Ruhi_72925 We lost our home 😭

[Sandeep Kumar @12th_kumar]

@siya_twt_ Verilog

[Sandeep Kumar @12th_kumar]

Implemented 2×2 Matrix Multiplication on a 32-bit 5-Stage Pipelined MIPS Processor using Verilog HDL on Basys 3 FPGA.

Successfully executed matrix operations with real-time FPGA output visualization using seven-segment displays.

#FPGA #Verilog #MIPS #VLSI #RTLDesign

[Sandeep Kumar @12th_kumar]

@S2SmeX Same brotha !✋

[Sandeep Kumar @12th_kumar]

@S2SmeX “Show me your friends’ projects 😏. Mine are building things worth flexing.”

[Sandeep Kumar @12th_kumar]

@S2SmeX Yes ✋🙂‍↕️

[Sandeep Kumar @12th_kumar]

@richnanophd That’s a really solid suggestion. I was already hitting BRAM limits on Basys 3, so mapping 2D convolution into serialized 1D MAC operations with weight reuse makes a lot more sense now. Definitely going to experiment with line buffers and sliding window optimization next.

[Sandeep Kumar @12th_kumar]

Spent days debugging instruction decoding,Built my custom pipelined MIPS processor on Basys 3 FPGA with a working dot-product accelerator.

After endless debugging, finally got the correct hardware output: 0032.
Now I want to make it dynamic and want to cnn in it can anyone help

[Sandeep Kumar @12th_kumar]

@dwasf79850 That’s seriously ahead of its time. Dynamic hardware acceleration on Virtex boards must’ve been wild to experiment with back then. Feels like the early roots of what people now market as heterogeneous computing and AI accelerators.

[Sandeep Kumar @12th_kumar]

@MaxClerkwell Absolutely. I’m cleaning up the repo and documentation properly first so it’s easier for students to follow. I’ll share the GitHub link here as soon as it’s ready.

[Sandeep Kumar @12th_kumar]

@dwasf79850 MIPS on Spartan FPGA is such a solid learning experience. Those boards introduced an entire generation to real hardware design. What project did you build on it?

[Sandeep Kumar @12th_kumar]

Show me your projects
I am making a mips 32 processor tell me how to make it representable 😭

[Sandeep Kumar @12th_kumar]

Doremon summer

[Sandeep Kumar @12th_kumar]

Lost my home 🏡

[Sandeep Kumar @12th_kumar]

You don't have a better evening than me 😏. If you had the show me ??

[Sandeep Kumar @12th_kumar]

When was the last time you were happy? 🥹I bet you didn't have this beautiful view 🪟