Mike Goldsmith

Semiconductors. Smartphones. Sake. Tequila. LEGO. Pokemon Go.

Views expressed are my own and do not represent those of my employer.

[Mike Goldsmith @Darth_Goldsmith]

@RudolfGottfried @0x0SojalSec It is the same generation and core count for NPU in both M4 and A18/P, so presumably if it can run on one it can run on the other. Memory limitations of iPhone notwithstanding.

[Mike Goldsmith @Darth_Goldsmith]

@aschilling I guess sLVT and iLVT were taken? /s

[Mike Goldsmith @Darth_Goldsmith]

@OneRaichu @aschilling No, the image is meant to show that the carrier wafer used above the signal side metals has improved (lower) thermal resistance. Really should not be dependent on wafer thickness. Haven't read the paper yet.

[Mike Goldsmith @Darth_Goldsmith]

@hmph29759351 @IanCutress Thanks for posting the source of this, I was confused why Huawei was on the chart at all.

[Mike Goldsmith @Darth_Goldsmith]

@SaintjohnD @IanCutress It hasn't. This is comparing the claimed density of logic-folded (3D) SMIC vs the true SMIC density. The whole red line is marketing fluff, but I don't think Ian is interpreting that uptick correctly. To me looks more like they plan >2 decks at that point in time.

[Mike Goldsmith @Darth_Goldsmith]

@lithos_graphein Need to start w/ packaging. That or nodes older than FinFET, so there is some counterweight to the China fabs that scooped up all the old 6" and 8" equipment. Anyone doing 0.25u on 12"?

[Mike Goldsmith @Darth_Goldsmith]

@lithos_graphein @SemiAnalysis_ M2 also has tracks removed, so more likely some form of LELE, but tighter pitch than the ~45nm at M3.

[Mike Goldsmith @Darth_Goldsmith]

@lithos_graphein @SemiAnalysis_ CDU for M2 or M3? M0/M1 are using SAQP, M3 might be LELE instead of SADP. M2 from this cut IDK.

[Mike Goldsmith @Darth_Goldsmith]

@Rebrickable Great naming

[Mike Goldsmith @Darth_Goldsmith]

@Coldwood1026 @zhaphod @IanCutress ... and since the Hygon parts reuse the SP3 socket they also reuse the platform, which gave the Server MoBo players more market to sell into than "just" AMD.

[Mike Goldsmith @Darth_Goldsmith]

@Vengineer It could be one die given the gap between top and bottom pair. One die rotated 180* connects to itself over high-density interconnect (possibly CoWoS), then two of those modules connect via substrate. Similar to MI200/250.

[Mike Goldsmith @Darth_Goldsmith]

@HendyBears @yonann Came to post this, not disappointed it's already here.

[Mike Goldsmith @Darth_Goldsmith]

@Reptalicant Maybe we mean the same thing. I read "4LPX" and assume you mean SF4X, which is the 3rd (ish) gen of SF4 (which yes, used to be S4LPE). If what you meant was "4LPX is S5LPP with slightly better transistors" and a Qualcomm marketing term, then I agree.

[Mike Goldsmith @Darth_Goldsmith]

@Reptalicant Also Qualcomm don't call it SF4X (at least not at launch), but they do call in "4nm". Blame marketing.

[Mike Goldsmith @Darth_Goldsmith]

@nMonster_Inc @aschilling

[Mike Goldsmith @Darth_Goldsmith]

@DrFrederickChen @Asset_sMind @lithos_graphein Yes, in this sample you can see both the TNCs and Gate metal (And Epis, and VCGs). Definitely a thicker cut than the I tell one, but this is more what I would expect to see. Assume CPP is 50nm, that's about 2/3 the thickness in the SF2 case, in Intel it would be 1/3 or less.

[Mike Goldsmith @Darth_Goldsmith]

@bubbleboi @lithos_graphein @highyieldYT

[Mike Goldsmith @Darth_Goldsmith]

@DrFrederickChen @Asset_sMind @lithos_graphein Sorry, not M1, that's at the top. Empty ILD is for V0 here, I guess. But no V0 or VCG/VCD shown?

[Mike Goldsmith @Darth_Goldsmith]

@DrFrederickChen @Asset_sMind @lithos_graphein might just be due to the cut location. Depop M0 for the other track locations - there is no M1 either, or shadow of it (just the resulting ILDs), so the TEM prep must be very thin.