Morpheus

Finding Eternity

[Morpheus @Dreaming_Man2]

@harukaze5719 They're only internal projections inferred from "expected" release timelines, anyone can do that

[Morpheus @Dreaming_Man2]

Epyc 9996 Geekbench 7
https://t.co/WuTrBESS5i

[Morpheus @Dreaming_Man2]

MD2190

[Morpheus @Dreaming_Man2]

AT2

[Morpheus @Dreaming_Man2]

Medusa2
FP10

[Morpheus @Dreaming_Man2]

FF5 Socket Simulation CPU

[Morpheus @Dreaming_Man2]

AMD Eng Sample 100-000001930-12_Y 6C/12T

0807gpufull
https://t.co/je0quugzCD

[Morpheus @Dreaming_Man2]

AMD Eng Sample 100-000001930-01_N 6C/12T
AMD GBR-FF6-SKT
Gainsborough

0728tro
https://t.co/q8WHrcJpz7

[Morpheus @Dreaming_Man2]

@sudoingX Achieving high memory bandwidth without the obvious area penalty can be only done with advanced packaging, which sacrifices modularity offered by DIMM/CAMM.

There are possible solutions with optics and CXL mem but we still have to wait for a while for mass adoption.

[Morpheus @Dreaming_Man2]

@sudoingX It requires a lot of memory PHY shoreline on die + a lot of wires on both the package and PCB + the engineering efforts to validate such complex things. Plus, a lot of the modules (DIMM/CAMM/etc.) don't offer much bandwidth compared to HBM/GDDR which require a lot of wires.

[Morpheus @Dreaming_Man2]

@SquashBionic @pers0naluni0n That's... more grim than I thought. Either way they better catch uo

[Morpheus @Dreaming_Man2]

@pers0naluni0n @SquashBionic It's not competitive at all.