Jevonslee👨‍💻

Sales Executive, Semiconductor CIM Solutions, Data Analysis. worked at Intel, Amkor Technology; Co-Founder of VCIMSOFT

[Jevonslee👨‍💻 @JevonsLi]

FDE is about deploying AI into the existing operating model. AI Native is about redesigning the operating model around AI.

[Jevonslee👨‍💻 @JevonsLi]

@YesterdayBigcat 街道城管，都是无业人员～

[Jevonslee👨‍💻 @JevonsLi]

@chengxuzhang2 @antiAIvo 他肯定说是元宝

[Jevonslee👨‍💻 @JevonsLi]

@xiongchun007 那锅谁来背

[Jevonslee👨‍💻 @JevonsLi]

@jessyshen 我在 Intel 没碰到你说的事情！

[Jevonslee👨‍💻 @JevonsLi]

@gdb ChatGPT Work is my all-in-one digital assistant. From video editing and planning to precise multilingual translation, daily financial management, scheduling, and capturing daily core insights, it fully covers my operational and administrative needs.

[Jevonslee👨‍💻 @JevonsLi]

World Cup 2026: Finals
https://t.co/xXyvTialKS

[Jevonslee👨‍💻 @JevonsLi]

Anthropic's Katelyn Lesse & Angela Jiang: Building an Ecosystem, not a W... https://t.co/y1pwkpcIf7 来自 @YouTube

[Jevonslee👨‍💻 @JevonsLi]

https://t.co/0mBA8dxe77

[P Equity Research 📰 @pequityresearch]

I highly recommend listening to this podcast. SUSS MicroTec's CEO, Burkhard Frick, got interviewed. A lot of key points made here:

> SUSS has successfully qualified and delivered its initial machines to the third major player, SK Hynix, looking to capitalize on upcoming industry capacity expansion.

> SUSS recently shipped its first rectangular "panel-based" packaging scanner to TSMC $TSM for a pilot line. Transitioning from round wafers to rectangular panels optimizes surface area utilization and supports larger overall chiplet modules, though a true volume phase is expected closer to 2030.

> SUSS acknowledges that competitors like Besi hold the lead in Die-to-Wafer hybrid bonding speed. However, SUSS distinguishes itself as the only manufacturer capable of offering a single machine handling both Die-to-Wafer and Wafer-to-Wafer solutions. SUSS is actively working to improve machinery throughput ahead of the expected 2027–2028 market volume phase.

> SUSS is actively evaluating optical and laser technologies for CPO to help lower data center power consumption. Frick emphasizes that glass-based substrates are undergoing heavy R&D but are not yet production-ready for high-volume manufacturing. In mass production, losing even fractions of a percent in yield costs millions, so glass must clear incredibly high maturity hurdles and states "we are a few years away." While companies like Intel and LG are driving interest, and German firm LPKF Laser & Electronics is active with its Laser-Induced Deep Etching (LIDE) technology, the industry remains cautious.

> Memory business has evolved from a volatile, spot-price-driven market to one with more sustainable growth, although he anticipates that the current rapid growth will eventually "relativize" as production capacities stabilize.

[Jevonslee👨‍💻 @JevonsLi]

@WangNextDoor2 假的。

[Boris Cherny @bcherny]

As engineering, product, design, DS, etc. melt into a new kind of role, I was reflecting on what roles might look like in the future. For example, when I look at the Claude Code team I see what I think is five archetypes:

1. Prototyper: comes up with brand new ideas; churns out many ideas, most of which don't ship
2. Builder: quickly turns a prototype/idea into production-grade product/infra
3. Sweeper: cleans up the UI, simplifies the code and system, unships, optimizes performance
4. Grower: takes a product that has been built and iterates on it to improve Product-Market Fit
5. Maintainer: owns a mature system to make it secure, reliable, fast, and efficient as it scales

Many people span across 2 roles, and sometimes 3 roles. I also notice that these roles are not really tied to job function -- eg. across Anthropic, some designers match category 1, some 2, some 3; same for engineers, PM, DS.

A healthy team needs a mix of these, depending on the product:

- A product that is new and pre-PMF needs people that are strong at 1+2+3
- A product that is growing and has found PMF needs 2+3+4 and some 5
- A product that has strong PMF needs 3+4+5 and some 2

Maybe product roles of the future will look more like this, and less like the domain-specific roles of today?

[Jevonslee👨‍💻 @JevonsLi]

Designing Math ft. Grant Sanderson (3Blue1Brown) I Config 2026 https://t.co/e4tlMXDii8 来自 @YouTube

[Jevonslee👨‍💻 @JevonsLi]

2026 Nvidia Annual Stockholder Meeting https://t.co/2qx0WFF3gV 来自 @YouTube

[Tibo @thsottiaux]

Codex **had** a bug. Fixed.

More feedback. Better product. Keep it coming.

[Jevonslee👨‍💻 @JevonsLi]

1/

The most easily misunderstood aspect of CXMT’s IPO:

It is not about China's DRAM leader going public.

Rather, it is a financial statement at the peak of a cyclical upturn being packaged as a structural catch-up.

2/

The DRAM market is currently abnormal.

HBM is consuming wafer capacity. AI servers are consuming DDR5. Major customers are locking in long-term supply. Even standard DRAM is being squeezed into shortages.
When prices surge, the financial statements of laggards suddenly look beautiful as well.

3/
Therefore, when looking at CXMT, the first thing to look at is not revenue growth.

Break down three things first:

How much did bit shipment grow?

How much did the ASP increase?

How large is the unit bit cost gap compared to the top three manufacturers?

If profits are primarily driven by ASP, that is not a moat.

That is just the wind.

4/

And this round of wind is incredibly strong.

The Shanghai Stock Exchange project has been confirmed: CXMT Technology Group Co., Ltd. has applied for the STAR Market, planning to raise 29.5 billion RMB.

The market also happens to be playing in its favor.

The DRAM shortage of 2025–2026 is not a minor cycle like consumer electronics inventory replenishment.

Behind it, AI has completely reordered the entire memory stack.

5/

The problem is:

Cycles can provide revenue. Policy can provide valuations. Domestic substitution can provide a narrative.

But none of them can automatically grant HBM yield rates.

Nor can they automatically erase the DDR5 unit cost gap.

6/
What CXMT truly needs to prove is not "whether it can sell DRAM."
It has already proven that.

The real questions are:

When prices stop climbing vertically, how much gross margin will it have left?

When customers transition from DDR/LPDDR to HBM, will it be qualified to capture that highest-value tier?

7/

HBM is the strangest omission in this IPO narrative.

If CXMT is the core asset for China's AI memory self-reliance, HBM should be the strategic center.

Yet, what can currently be publicly confirmed is only the existence of this 29.5 billion RMB fundraising project.

As for how much HBM actually accounts for in the investment breakdown, we need the page numbers of the prospectus to speak for themselves.

Without page numbers, emotion cannot substitute for evidence.

8/

There is an even colder point to consider:

Looking at consolidated net profit is useless.

IPO investors need to look at net profit attributable to shareholders of the parent company (net income to parent).

If the majority of the economic benefits of core manufacturing assets remain with minority shareholders, the high profit margins on consolidated financial statements will not translate into high returns for public shareholders.

This is not an accounting detail.

This is the gateway to valuation.

9/

CXMT’s advantages are real:

It is China's only large-scale, strategic asset for commodity DRAM. It has Hefei’s long-term capital backing it up. Local packaging and testing, industrial gases, wafer recycling, and equipment supply chains are built around it. Domestic customers have a clear need for substitution.

This is no ordinary semiconductor company.

10/

But its shortcomings are equally rigid:

The cost gap still needs to be closed. HBM still needs to catch up. The attributable profit framework must be scrutinized. Affiliated customers must be scrutinized. The pricing cycle must be scrutinized.

The strategic value of Chinese DRAM does not mean every share of IPO equity is inherently cheap.
11/
My judgment on the CXMT IPO comes down to a single sentence:
This is a strategic asset going public at the absolute peak of a powerful cycle.

A strong cycle will amplify its progress. It will also mask its shortcomings.

The most dangerous way to buy in is to mistake a tailwind for capability.

12/

The real thing to track is not how much it gains on day one.
It is three numbers:
Gross margin after ASP cools down.
HBM yield rates and customer adoption.
The ratio of net profit attributable to the parent company versus consolidated profit.

Before these three numbers come to light, it is not that you cannot look at CXMT.

It is that you cannot look solely at headline growth.

[Jevonslee👨‍💻 @JevonsLi]

John E. Bowers（约翰·鲍尔斯）是全球光电子学、光子学以及半导体硅光子领域的顶尖科学家、物理学家和工程学家。他目前担任加州大学圣塔芭芭拉分校的杰出教授、Fred Kavli 纳米技术讲席教授，同时也是 UCSB 能源效率研究所的所长。

他最著名的成就之一，是将激光器和光电元件直接集成在硅衬底上，这一突破性进展为现代高速数据通信、数据中心以及下一代光子集成电路（PIC）奠定了关键基础。

John Bowers教授将共同探讨正在颠覆 AI 基础设施与现代数据中心的核心技术。Bowers 教授在节目中深入阐述了为什么“数据传输”已成为现代计算的核心挑战、光通信如何打破传统电互连的物理瓶颈，以及为何光信号正越来越多地被用于连接处理器、服务器乃至整个数据中心。

一同回顾了硅光子学的起源，从早期的光通信研究，到如今能够利用成熟半导体工艺进行量产的集成光子器件的发展历程。Bowers 教授还分享了将激光器与硅材料结合时所面临的工程挑战、推动异质集成（Heterogeneous Integration）取得突破的关键节点，以及长达数十年的研究如何最终推动硅光子技术走向全球规模的商业化落地。

紧接着，我们审视了人工智能（AI）日益增长的算力需求。在当前的 AI 时代，处理器之间的数据流转已经变得与计算本身同等重要。Bowers 教授解释了为什么带宽、功耗和互连密度正成为 AI 系统的核心瓶颈，以及光链路如何赋能下一代超大规模计算架构。

此外，还深入探讨了数据中心网络、光互连、共封装光学（CPO）、异质集成、半导体制造、光子集成电路（PIC）、电信技术、AI 硬件以及未来仓储级计算（Warehouse-Scale Computing）的发展趋势。在整期节目中，Bowers 教授站在行业前沿，为我们独家解读了光子学的技术演进如何重新塑造支撑现代计算的底层基础设施。

无论您是专注于硅光子、光通信、半导体工程、计算机架构、AI 硬件、数据中心设计、网络技术、集成光子学、电气工程，还是对计算的未来充满好奇，本期节目都将为您带来一场关于“驱动 AI 革命幕后关键技术”的深度技术探秘。

[Jevonslee👨‍💻 @JevonsLi]

Silicon Photonics and the Future of AI Scaling | John Bowers https://t.co/xo2mM1fBTI 来自 @YouTube

[Jevonslee👨‍💻 @JevonsLi]

Silicon Photonics and the Future of AI Scaling | John Bowers https://t.co/xo2mM1fBTI 来自 @YouTube

[Jevonslee👨‍💻 @JevonsLi]

@XieJackie 人家在吃面🍜