coolcoolcat

crypto and cat

[Macro_Lin ｜ 市场观察员 @LinQingV]

https://t.co/OopPFOP65S

[coolcoolcat @LUOROSA1]

@KobeissiLetter What a corrupted country. The President made insider trading publicly with no punishment.

[Fiona ❤️& ✌️ @nft_hu]

为何会提出光互连解决当前HBM封装的极限？
最本质的原因是：我们正在一步步接近HBM封装的极限。

一、物理规律的极限被逐渐触及：
极限1️⃣：垂直堆叠层数——已触顶
HBM的堆叠演进：HBM2（8层）→ HBM2E（8层）→ HBM3（12层）→ HBM3E（12/16层）→ HBM4（计划16–20层）。
每多叠一层，TSV（硅穿孔）的深宽比就要提高。目前16层的TSV深宽比约为20:1，这是电镀铜填充工艺的极限边缘——再往上，铜填充时气泡无法逸出，良率断崖式下跌。
更深的问题是热阻叠加。每层DRAM die的导热路径要穿越所有下层芯片才能到达散热器。12层堆叠时底层die的结温（junction temperature）比顶层高约15°C，20层时这个差距会超过25°C，已经超过DRAM工作安全边界。
这都导向一个事实——垂直方向的物理扩展空间已所剩无几。

极限②：硅中介层岸线——已触顶
GPU的「岸线」（shoreline）是GPU die四周边缘的物理周长。HBM堆栈通过硅中介层与GPU并排，HBM的数量上限就是：GPU周长能容纳多少个HBM接口宽度。
假设GPU die最终做到一个reticle极限，周长约为130mm，单个HBM4堆栈接口约需4mm，理论上限约为32个堆栈——但实际上电源/信号走线、角落利用率等因素会把这个数字压到16–20个以内。

极限③：带宽密度（单位面积IO数）——接近极限
Microbump的物理极限大约在25–30μm pitch，低于这个数字，焊锡球的表面张力和对准精度无法维持量产良率。

极限④：功耗密度——这是最被低估的极限
HBM3E每栈满载功耗约15W，8栈就是120W，加上GPU本身的600–700W，整个封装的功耗密度已经超过100 W/cm²，相当于火箭发动机喷口附近的热流密度。
散热才是最硬的物理墙。
HBM越叠越高，散热路径越长，这是垂直堆叠无法回避的热阻叠加问题，与材料科学的边界直接碰撞。
—————————————————————————

二、光连接的解法
电信号传输本质上是在用「极短距离」这个物理条件换取优势。
光的优势恰好在电的弱点处显现——光信号的带宽与距离几乎无关。当GPU与HBM的物理间距被迫增加，光互连的相对优势就从「理论上可行」变成「工程上合理」。
—————————————————————————
三、目前技术架构的可能形态
方案A：光学Bridge芯片
在硅中介层中嵌入硅光子波导层，GPU与HBM之间的信号不再走铜线，而是走片内波导。距离仍在毫米级，但打破了「必须紧邻」的约束，允许HBM在中介层上远离GPU边缘排列。
这是Ayar Labs（与Intel合作）的TeraPHY路线，已在2024年实现单chiplet 2Tbps光I/O，且可3D堆叠于逻辑芯片下方。

方案B：CXL over Optics（推理情况不合适）
将多个HBM堆栈聚合为独立的记忆体池模块，通过CXL协议与GPU通信。距离可达几厘米至数十厘米，直接接入背板。这不是HBM专属光互连，而是把HBM变成CXL记忆体节点。
延迟代价：每次E→O→O→E转换约增加5–10ns，相对于DRAM本身的~150ns访问延迟，约增加3–7%，在大模型训练的流式访问模式下可接受，但推理场景（延迟敏感）会更在意。

方案C：3D光学垂直互连（最激进）
将HBM置于GPU正下方，利用垂直光学通孔（Optical Through-Silicon Vias，OTSV） 实现Z轴方向的光互连。这在理论上消灭了岸线限制（HBM直接在GPU下方大面积铺展），同时保持极短传输距离。

方案D：光子织网
把光子互连fabric做成一个独立的2D芯片层，像三明治一样插在GPU和HBM（或其他加速器）之间，所有芯片通过这层光子层通信。它并不限定是HBM，而是一个通用的光互连基板。
—————————————————————————
四、这个方案的难点：激光源
这是目前工程界最头疼的问题。
硅不能发光。硅光子可以导光、调制光、探测光，但无法产生光。今天所有硅光子方案的激光源都是III-V族化合物半导体（InP、GaAs基材料），需要外置激光器，通过fiber coupling耦合进硅波导。

这带来：
可靠性问题：激光器是光互连系统中寿命最短的组件
良率问题：光纤与波导的耦合对准精度要求亚微米级，大规模封装良率极低
成本问题：III-V激光器目前仍比硅便宜不了多少，难以摊薄
功耗问题：激光源本身的电光转换效率约30–40%，是额外的能耗来源
————————————————————————
五、解决路径：
1️⃣直接在硅上外延生长III-V材料
Intel、MIT林肯实验室、UCSB都在研究，但良率与可靠性尚未达到量产标准。
2️⃣另一条路是量子点激光器直接长在硅上，理论上可行但仍是实验室阶段。
AXT（AXTI）的潜在价值就在这里——其磷化铟（InP）基片是高性能光互连激光器的关键衬底材料，这条需求链条目前仍处于早期。
————————————————————————
六、时间线
2026–2027：板级CPO（GPU与光引擎共封装）进入量产，主要用于scale-out网络，不直接涉及HBM
2027–2029：光学Bridge方案开始进入高端AI加速器概念验证，HBM可能扩展至更远位置但仍在同一封装内
2029–2032：CXL over Optics的记忆体池化开始规模部署，HBM功能性分离
2032+：真正意义上GPU-HBM光互连作为标准封装方案，仍存在不确定性

[Jukan @ICML @jukan05]

Breaking the "Memory Wall": Optical Interconnects Emerge in GPU–HBM Packaging

As a solution to the "memory wall," one of the chronic challenges in AI semiconductors, the memory and packaging industries at home and abroad are weighing an approach that decouples the GPU and high-bandwidth memory (HBM) and packages them separately. The core idea is to move the HBM—until now mounted right next to the GPU—a certain distance away, and bridge the gap with light (optics), allowing several times more HBM to be installed than is possible today.

On the 22nd, a researcher at a major domestic memory maker said, "We're currently struggling to expand HBM bandwidth and capacity, so we're discussing with customers a plan to overcome the GPU's shoreline limit through optical interconnects and mount more HBM." Shoreline refers to the length of the chip's perimeter.

In today's AI computing environment, the key factor dragging down compute efficiency is the data transfer speed of memory chips. While GPU performance has grown by leaps and bounds with each generation, the speed at which memory stores and supplies data has failed to keep pace—creating a structural performance barrier, the memory wall. The arrival of HBM, with its wide data pathways, put out the immediate fire, but critics continue to point out that bandwidth and transfer speeds still fall short of handling the explosive growth in AI compute.

Until now, the industry has focused on stacking HBM ever higher to increase memory capacity and bandwidth within a confined footprint. But as stack counts climbed past 12 and 16 layers toward 20 and beyond, process difficulty rose exponentially. The technology hit physical limits, including the growing difficulty of meeting fixed height specifications. Vertical stacking has reached an inflection point—so much so that the JEDEC standards body has relaxed its HBM height specifications.

The bigger problem is that if stack counts can't be raised, the alternative is to add more HBM horizontally around the GPU—but that, too, is impossible. In the current 2.5D packaging structure, the GPU and HBM are mounted tightly together on a single substrate. Within this structure, the number of HBM units that can be placed is strictly limited by the finite length of the GPU chip's perimeter—its shoreline. Even when more HBM is desired, there is physically no room to place it, leaving the industry in a structural deadlock.

The alternative now emerging across the semiconductor industry is to separate the GPU and HBM and package them independently. It overturns the conventional chip-design principle that components must sit close together to minimize data transfer time. Instead of keeping the two chips adjacent, the approach spaces them apart and links them with overwhelmingly fast optical signals to overcome the added physical distance.

Placing the HBM slightly away from the GPU within the board frees the design from the GPU's shoreline constraint. With the spatial limitation gone, far more HBM can be spread out laterally and packed into the board—several times more than today—without having to push stack heights to extremes. This means the total memory capacity and data bandwidth of the AI accelerator system would expand dramatically, on a scale incomparable to current systems.

"Discussing Placing HBM Beneath the GPU"… Form Factor Could Change

The industry is now producing a range of architectural design proposals over where exactly to place the HBM within the GPU board.

The same memory researcher said, "Options under discussion range from broadly utilizing the space immediately around the GPU to isolating the HBM beneath the GPU board." He added, "In the latter case—isolating it beneath the GPU board—the motherboard would have to be extended lengthwise, so we're discussing even an overall form-factor change with the GPU maker." Specifically, the HBM might surround the GPU from several centimeters away, or a separate HBM zone might be created in the center of the board.

"We're keeping every possibility open as we discuss the optimal layout," he said. "Nothing has been confirmed as an official roadmap yet, but as part of preliminary research toward next-generation AI accelerators, we're in talks with our partners."

The outsourced semiconductor assembly and test (OSAT) industry is also watching this trend closely. An executive at a global OSAT firm said, "Optical interconnects are a clear trajectory. The only question is timing," predicting that "rack-to-rack and server-to-server links will go optical first, and then chip-to-chip connections within the board will follow." He added, "The larger units will be connected by light first, but optical research is moving so fast that it may not be that far off."

Technically, the optical-interconnect technology linking GPU and HBM shares the same underlying principle as the technology connecting server to server inside a data center. The difference is the high technical barrier of shrinking optical-conversion technology—once used for communication between large pieces of equipment—down to the microscopic scale of a single board and chipset.

An executive at a domestic developer of co-packaged optics (CPO) components explained, "As HBM stack heights approach their limit, the industry is discussing spreading the memory out laterally to maximize how much can physically be mounted." He added, "The principle is the same as conventional data-center optical interconnects, but HBM optical links that have to operate within a confined board space require optical components to be miniaturized to far smaller sizes and far higher integration density—so the technical difficulty is greater."

[Macro_Lin ｜ 市场观察员 @LinQingV]

华为昇腾2026年芯片营收预计从75亿美元跳到120亿美元，同比+60%。FT报道大部分订单集中在昇腾950PR，字节、腾讯、阿里都在抢。与此同时，DeepSeek V4定价页写了一行灰色小字：受限于高端算力，目前Pro的服务吞吐有限，预计下半年昇腾950超节点批量上市后，Pro价格会大幅下调。

一个模型公司，把自己API的降价节奏明确锚定在另一家公司的芯片量产时间表上。DeepSeek没有说”等NVIDIA供货改善后降价”，它选择的锚点是昇腾950。在DeepSeek内部的成本模型里，昇腾已经从”兼容适配”变成了”产能依赖”。这种绑定深度在国内AI产业里没有先例。

几百个超节点意味着什么量级？昇腾超节点支持64卡步长扩展，最大8192卡全互联。即使按最保守的64卡/节点估算，几百个节点就是上万张昇腾950。单DeepSeek一家的需求，就能撑起一条可观的供应链订单流。

沿着供应链从芯片往外走，几个关键环节的供应商卡位值得梳理。

先进封装，盛合晶微。昇腾芯片前道由中芯国际完成，后道2.5D/3D封装据业内共识由盛合晶微承接。据产业链信息，华为与盛合晶微签订了多年期合约锁定产能。据招股书及调研数据，盛合晶微在2.5D硅基封装规模化量产领域国内市占率85%，全球具备这一能力的仅有台积电、三星、英特尔和盛合晶微四家。昇腾芯片需要的大尺寸2.5D多芯片集成封装，大陆目前仅盛合晶微具备规模化量产能力。今年科创板最大IPO，募资约50亿，发行市盈率195倍。

光模块，华工科技。昇腾超节点是全光互联架构，CM384里NPU和光模块的比例是1:18。华工科技是华为800G光模块核心供应商之一，在华为体系内份额领先。两家公司都在武汉，合作始于2005年，华为金牌供应商。技术路线上，华工的硅光LPO方案天然适合昇腾这种封闭集群场景，800G出货中硅光占比已超70%。光迅科技也有份额，但基本盘在电信市场，AI算力场景的增量弹性弱于华工。值得一提的是华工的上游基本自己解决了，硅光芯片全自研，EML芯片通过参股的云岭光电覆盖，唯一外部依赖是Marvell/博通的高功耗PAM4 DSP芯片，而LPO方案恰恰绕开了这层依赖。

存储（HBM），华为自研。昇腾950PR搭载自研HBM，分HiBL 1.0（128GB/1.6TB/s）和HiZQ 2.0（144GB/4TB/s）两个版本。三星和SK海力士的HBM受出口管制约束拿不到，华为走了定制化路线，HBM通过封装载板走线连接而非传统硅中介层直连，和标准HBM在物理接口上有差异。DRAM颗粒来源市场普遍推测指向长鑫存储，但双方均未公开确认。

高速连接器，华丰科技。昇腾950PR互联带宽2TB/s、功耗约600W，对背板连接器的要求极苛刻。据产业链信息，华丰科技是昇腾高速背板连接器的核心供应商，市占率居前。

PCB和载板，深南电路同时覆盖高端PCB和IC载板两个环节，兴森科技在ABF载板有份额。上游CCL看生益科技。

一个容易产生误解的环节是OCS光交换。昇腾超节点的”全光互联”用的是华为自研的灵衢互联技术，本质是基于光模块的点对点直连，拓扑固定，不需要OCS的动态光路重构。集群层面（多个超节点之间）用UBoE或RoCE以太网组网，华为推荐UBoE。所以昇腾放量对OCS产业链的直接拉动有限，OCS的增量客户主要在谷歌和NVIDIA生态。

供应链弹性是短期的事，更值得关注的是背后一个结构性拐点：国产AI算力的需求侧，正在从”政策驱动采购”转向”市场化产能消化”。DeepSeek愿意把自己的降价空间押在昇腾产能上，说明国产算力的性价比已经跨过了某个临界点。当需求侧的拉动力从行政指令变成商业利益，供应链各环节的估值锚就该重新校准了。

DeepSeek V4在昇腾950超节点上8K输入场景实现TPOT约20ms、单卡Decode吞吐4700TPS（离线推理模式，不含Serving调度开销）。这个数字已经具备商业化部署的实用性。当国内最强开源模型把昇腾当成默认优化起点，其他模型厂商跟进是顺水推舟的事。昇腾过去缺的就是一个重量级模型厂商带头用起来，DeepSeek补上了这一环。

[Chris Barber (in SF and at AIE) @chrisbarber]

https://t.co/Z5V4Li4QFE

[coolcoolcat @LUOROSA1]

I used to believe America was a beacon—not because it was perfect, but because it had the capacity to self-correct. Then a man found liable for sexual abuse and convicted on 34 felony counts walked back into the Oval Office. A clown, a profiteer, a man driven not by service but by money. The light has gone dark.

[coolcoolcat @LUOROSA1]

@KobeissiLetter Dont worry, Trump will say “something big” before the market open

[coolcoolcat @LUOROSA1]

@AirdropGlideApp That's the typical thing of what comos eco developers would do.

[coolcoolcat @LUOROSA1]

@KobeissiLetter Trump is a fxxking clown

[Tw93 @HiTw93]

https://t.co/RTkJ3NQKeS

[coolcoolcat @LUOROSA1]

@magnacarterio @bankrbot deadcoin

[coolcoolcat @LUOROSA1]

熊猫速汇送你一次免费汇款机会
https://t.co/Xk2XhfYJhK

[coolcoolcat @LUOROSA1]

@0x_xifeng 纯粹扯淡的数据

[coolcoolcat @LUOROSA1]

@aztecnetwork coool

[Aztec @aztecnetwork]

Get ready for the biggest Rabbit Hole of the year (and quite possibly your life).

Notifications on.
https://t.co/TkvAc2Xo2E

[coolcoolcat @LUOROSA1]

@NexusLabs aaa

[Nexus @NexusLabs]

Gridcrews are live.

→ Pick your path. Choose SYN, ACK, or FIN.
→ Compete as a crew. Earn collective rewards.
→ One choice. No switches. 15 days of action.

Start proving — together: https://t.co/OTwTp9PU7j
After you've selected a Crew, start questing: https://t.co/4tytEdzzbK

[coolcoolcat @LUOROSA1]

@NexusLabs llll

[Nexus @NexusLabs]

1/ In just a two years, Nexus has gone from a 1 Hz prototype to a global zkVM powering millions of verifiable computations.

Here's our origin story:

https://t.co/0ZIDU1rCVd