QuickSilicon

We at QuickSilicon are here to revolutionise how the semiconductor hires its best talent.

[Suresh Kini @Suresh_Kini_09]

Really excited to share my progress on QuickSilicon! Completed Day 9 of 21 Days of RTL course! https://t.co/ppeSrJTCZA ##21daysofrtl @QuickSilicon

[QuickSilicon @QuickSilicon]

Tik-Tok... 📷Prices for all QuickSilicon courses go up on June 15th! Click https://t.co/VizcEHFCqO
#designverification #QuickSilicon #python #HardwareDesign #vlsi #TechCourses #VIsiDesign #VIsiCourses #SystemVerilog #RTLDesign #ElectronicsEngineering #ProcessorDesign

[QuickSilicon @QuickSilicon]

At QuickSilicon, we're making hardware design everyone's thing—no matter what you do, let's geek out together! Oh and don't forget, prices of all the courses are going up on June 15th, 2024!

#designverification #QuickSilicon #python #HardwareDesign #vlsi #TechCourses #RTLDesign

[QuickSilicon @QuickSilicon]

Join us on this exciting adventure, where learning is immersive, hands-on, and tailored to equip you for success in the fast-paced world!

#QuickSilicon #HardwareDesign #vlsi #TechCourses #vlsifundamentals #VlsiDesign #VlsiCourses #SystemVerilog #RTLDesign #ElectronicsEngineering

[QuickSilicon @QuickSilicon]

Back in 1971, while tinkering with a calculator, Intel engineer Marcian Hoff had a lightbulb moment: "Hey, what if we jammed all these functions onto one tiny chip?" And just like that, the microprocessor was born!

#microprocessor #innovation #tech #QuickSilicon #HardwareDesign

[QuickSilicon @QuickSilicon]

Accelerate your hardware design verification process with the power of Python!

#designverification #QuickSilicon #python #HardwareDesign #vlsi #TechCourses #vlsifundamentals #VlsiDesign #VlsiCourses #SystemVerilog #RTLDesign #ElectronicsEngineering #ProcessorDesign

[QuickSilicon @QuickSilicon]

When you take a day off and the tester decides to "debug" the code. 😑

#QuickSilicon #HardwareDesign #codermemes #funny #vlsi #TechCourses #techmemes #developer #vlsifundamentals #VlsiDesign #VlsiCourses #SystemVerilog #RTLDesign #ElectronicsEngineering #ProcessorDesign #memes

[QuickSilicon @QuickSilicon]

Jack’s manager was furious when he realised that Jack had used ID values without a dummy flop.
Why is the dummy flop important for ID values?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verifications

[QuickSilicon @QuickSilicon]

Can you help Joe with a single line of synthesizable RTL to convert A into B?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Jack was puzzled to see the following waveform for an APB protocol. Can you help Jack list all the missing signals and the protocol violations?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Sam has come up with the following structure for implementing an asynchronous FIFO. Do you think he got it right? What should be the minimum size of the FIFO to avoid any overflow?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Given device 0 and 2 needs to transfer 8 bytes and device 1 needs to transfer 16 bytes.
Find the size of the fifo if all of the devices can potentially write 1 byte of data every cycle while the fifo can only pop once in 4-cycles?

#rtldesign #semiconductor #verilog #asicdesign

[QuickSilicon @QuickSilicon]

@chiakokhua @ico_TC I need to read this

[RetiredEngineer® @chiakokhua]

FREE!

"A Primer on Memory Consistency and Cache Coherence, Second Edition"

https://t.co/h1uK7sxF7t

[QuickSilicon @QuickSilicon]

Can you help Alex with the following problem?

Given inputs:
- clk
- reset
- x_i

Outputs:
- p_o

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

@kunksed Aren't these notes beautiful? Engineering can be creative too.

After all, why should MBAs have all the fun? :)

[QuickSilicon @QuickSilicon]

Taking good notes just don't help you focus better but also help you understand main concepts easily. Here's our take on few common digital design concepts.

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Is it signed or unsigned? Can you guess the output?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Jack was tasked to design a parameterised gray to binary converter. Do you think he got it correct?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification

[QuickSilicon @QuickSilicon]

Would you like to take a guess at the output of the following code?

#rtldesign #semiconductor #verilog #asicdesign #semiconductors #fpga #verification