Richard Platt

Intel Corporation's last "Innovation Master" - the avatar is a Scientific Demon, the Intel Innovation Demon

[Fred Chen @DrFrederickChen]

It was said here that on February 25, 2026, multiple semiconductor industry outlets reported that SMIC has successfully produced early 3-nanometer test wafers. https://t.co/3nXxPMB2e0

[Fred Chen @DrFrederickChen]

ASML Q1 2026 Earnings Call Transcript: https://t.co/LpmwKmZG5v
Customers who ordered High-NA EUV are expected to test whether it can work for real product. Thus, it's not a shoo-in.
Immersion systems are ordered along with EUV systems, so DUV capacity is targeted much higher.

[Fred Chen @DrFrederickChen]

No defect‑free process window is observed for Metal 0 logic PnR, for any High-NA EUV dose and focus even at the 24 nm pitch. https://t.co/61Lg6iljb0

[Fred Chen @DrFrederickChen]

Intel/Synopsys: Buried multilayer (ML) defects in EUV masks continue to pose a significant challenge to imaging fidelity and yield in 0.33 NA EUV lithography.
It's going to be even harder with High NA which can resolve smaller defects.
https://t.co/7cqj54ztiX

[Fred Chen @DrFrederickChen]

This video summarizes the factors which fundamentally drive stochastic defectivity in EUV lithography.
https://t.co/KvwaPW0AUj

[Fred Chen @DrFrederickChen]

28 nm pitch (center-to-center) with High-NA EUV MOR has easily detected defectivity.

[Fred Chen @DrFrederickChen]

Restates some points I made in my EUV Substack. The stitching and die height impact on productivity also should not be ignored. If this is true customer feedback, Intel 14A may need to give up High-NA or else risk delayed acceptance.

https://t.co/4eIElsZ0zg

[Fred Chen @DrFrederickChen]

Huawei announces 2026 Kirin at 238 MTr/mm2 with LogicFolding design, targeting 1.4nm in 2031.
https://t.co/eJboLroBqq

[Fred Chen @DrFrederickChen]

Huawei's claim of 238 Mtr/mm2 density implies something like CPP=48 nm, Cell height = 175 nm, comparable to N3E or 18A, but in actuality it could be looser than N+3, just using two bonded tiers of transistors.

[Fred Chen @DrFrederickChen]

TSMC doesn't need to aggressively shrink any pitches going from N3 to N2 to beat Intel and Samsung at the 2nm-class transistor density.

Source: https://t.co/TXGBU7Ksez (coverage starts at 5:00)

[Fred Chen @DrFrederickChen]

E. Musk: No one has near term plans to use High-NA EUV. "Half the chip for twice as much, for a gain that is relatively small."
https://t.co/X6xF74LHjV

[Fred Chen @DrFrederickChen]

Huawei recently announced its focus on tau scaling and LogicFolding for its chip design. The claim to increase transistor density mirrors the objective of using CFETs. How could they do this with hybrid bonding? That's discussed in this article.
https://t.co/iWjAZuOD6p

[Fred Chen @DrFrederickChen]

Here we examine the stochastic effects of EUV lithography for 32 nm line pitch, where, unlike metal interconnects, the lines are narrower than the half-pitch, as in DRAM word lines and bit lines. There is a significant impact on edge roughness. https://t.co/e5upru8byM

[Richard Platt @RPLATT101]

Microsoft released a set of prompts to help create a personalized AI Blueprint for your organization via @TDOttawa https://t.co/9gtqGGmREw

[Richard Platt @RPLATT101]

Brain Exercises Lower Risk of Alzheimer's Disease and Cognitive Decline, study shows https://t.co/888S3nMx2U https://t.co/6vHDfTRWX4

[Richard Platt @RPLATT101]

New Report from Stanford - Evidence Base on AI in K-12: 2026 via @TDOttawa https://t.co/3HnaeJIOx1

[Richard Platt @RPLATT101]

The invisible graveyard of AI tools in healthcare https://t.co/ZXnJhA0Iqk

[Richard Platt @RPLATT101]

Cognitive Offload ... and recommendations for Education - March 2026 Research via @TDOttawa https://t.co/wqYyRZrCoF

[Richard Platt @RPLATT101]

Dario Amodei Interview: 10 Lessons on AI, Safety, and What's Coming (2026) https://t.co/ZtYyHT4Jpo

[Richard Platt @RPLATT101]

Why (and How) Teachers Should Use Generative AI in the Classroom https://t.co/XyJopAySBV