J.Segura

Interested in technology, open source, FPGA, DIY and IoT among other things.

[GwenhaelGoavec @GwenhaelG]

I have updated openFPGALoader's @AlteraFPGA_ MAX10 support.
It's already possible to use a POF instead of svf.
Now it's possible to update UFM's sectors using a arbitrary binary file (no ihex or MIF convert).
A softcore's firmware may be updated like done for hardcore. 🎆

[J.Segura @SeguraEng]

@FPGA_Zealot @AlteraFPGA_ We have a small DECA community at telegram https://t.co/qZwJKuqFHC

[Hans Baier @[email protected] @hansfbaier]

The 1942 core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
I wrote a shell script which automates most of the gruntwork.
This is the first one ported with that script.
Thanks to the great work of @SeguraEng, it only took a couple of hours!

[Hans Baier @[email protected] @hansfbaier]

And the Toki core works too!🥳
@SeguraEng is the man!

[Hans Baier @[email protected] @hansfbaier]

@topapate A great many thanks to @SeguraEng for porting the core and the base framework!

[Hans Baier @[email protected] @hansfbaier]

The first core using the JOTEGO's (@topapate) framework is working on Xilinx FPGAs on the #MiSTeX #retrogaming #FPGA platform!

[Hans Baier @[email protected] @hansfbaier]

@SeguraEng (@somhi on GitHub) just got Toki, the second core of the @topapate jtcores working on MiSTeX! It already runs on Cyclone IV, and we still need to port it to Xilinx, but this is great news!

[J.Segura @SeguraEng]

@hansfbaier @RetroDriven @topapate @JLCPCB Many retro sellers have vga to SCART cables that will be compatible as you leaved I think that jumper to give 5V at pin 9 of DB15.

[Hans Baier @[email protected] @hansfbaier]

Everything works so far! The #MiSTeX #FPGA console is already playable. Tested: FPGA, RP2040-JTAG, VGA output, OrangePi-Zero2W communication. Untested: HDMI, audio, SDCARD.
Many thanks to @SeguraEng for his great suggestions for the schematic.
#retrogames #retrogamer

[J.Segura @SeguraEng]

Published source code for Arcade Pooyan on #Chameleon96 FPGA board https://t.co/oQhUH2KdaM

[J.Segura @SeguraEng]

Haven't forgot #Chameleon96 FPGA I bought at Arrow for 40€ three years ago. Has similar cyclone V as DE10 nano. Has some flaws like GPIO at 1V8, no direct clock signal, most GPIOs on HPS ARM side,...
Here I attached an FPGA Mezzanine to level shift the audio/video signals.

[J.Segura @SeguraEng]

@_atrac17 Yes please! It could be like a mini MiSTer but without those cores using SDRAM.

[J.Segura @SeguraEng]

@kbeckmann Not much familiarised with Litex/mingen, but I don't see in the code any I2C register configuration. Is it somewhere else that part or it just works without configuration at all? Also were you using stock SD card or have you modified preloader/uboot?

[J.Segura @SeguraEng]

@kbeckmann That's a start. Many thanks!

[J.Segura @SeguraEng]

@kbeckmann Where I can get your souce code for looking on how to initialise TDA chip?
I have ported Pooyan arcade core but using vga output at the moment

[J.Segura @SeguraEng]

@controlpaths Great! Do you have design in a repo?

[J.Segura @SeguraEng]

@CPU_FANS_MAX @ico_TC

[J.Segura @SeguraEng]

@nand2mario Pin 30 on MiSTer sdram modules is GND, so maybe better not to connect that pin on Sipeed dock.
Are the PMOD spacings according to Digilent's double PMOD specs? (should be 4x2.54 from pin to pin)

[J.Segura @SeguraEng]

Synthesized @topapate's JTKIWI binaries for MiST & SiDi. I don't have either of those but have been tested on both platforms. Just removed credits macros and
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
Find binaries here https://t.co/6esxge0spw

[Hans Baier @[email protected] @hansfbaier]

#MiSTeX now runs on the #RaspberryPi Zero!