Starting my 1 year FPGA journey today ⚡
Final year ECE student, building my way from RTL and digital design to real FPGA systems and eventually low latency hardware.
I’ll learn, build, break things, fix them and document it all.
Board: PYNQ Z2 🚀
From writing RTL to building AI agents for PCB design, things escalated quickly 😂
Huge milestone for @copperheadhq . Excited to be part of the journey and see what we can build next 🚀
@EnginTekinCodes@cerebras I may not have GPU inference stack experience yet, but I’m very good at learning hardware fast. Any chance you’re hiring interns too? 👀
Two pieces of RTL can do the same thing but synthesize into different hardware.
out <= up ? out + 1 : out - 1;
can infer two carry chains, while:
out <= out + (up ? 1 : -1);
can use one.
RTL isn't just behavior. It can influence the hardware you build.
https://t.co/BljR8QejGN