Spectral Compute

Nerds taming the green dragon with SCALE, our framework for compiling CUDA codebases for AMD GPUs, with support for more accelerated platforms coming soon.

[Spectral Compute @SpectralCom]

Full release notes: https://t.co/Xn3SrmNK7P

Join us on Discord: https://t.co/Aoq24AzJLd

[Spectral Compute @SpectralCom]

𝗦𝗖𝗔𝗟𝗘 𝟭.𝟳.𝟰 𝗶𝘀 𝗼𝘂𝘁.

Same CUDA code, same answers: single-precision maths now meets NVIDIA's documented error bounds. Fast-math division behaves as it does with nvcc, which can mean a very large speedup for division-heavy kernels. Occupancy fixes let code that sizes its own launches get more out of the GPU, and launches and 3D memory copies are faster too.

Download SCALE 1.7.4 for free, run it on your codebase, and tell us how it went on Discord.

[Spectral Compute @SpectralCom]

Come find us on Discord: https://t.co/pMrce4XTsm

[Spectral Compute @SpectralCom]

The most useful thing a SCALE user can send us is a bug report.

The CUDA API is huge. Large-scale projects depend on both documented and undocumented behaviours. The real target isn't described by the manual, it emerges when we try to run real workloads.

So what users actually hit decides which parts of the API we cover next and which fixes ship first.

If SCALE fails to build your code, gives wrong results, or runs slower than it should, tell us what broke and where on Discord. It moves your problem up the list.

𝗬𝗼𝘂𝗿 𝗳𝗮𝗶𝗹𝗲𝗱 𝗯𝘂𝗶𝗹𝗱 𝗶𝘀 𝗼𝘂𝗿 𝗿𝗼𝗮𝗱𝗺𝗮𝗽.

[Spectral Compute @SpectralCom]

AMD Instinct™ GPUs are incredible. A single AMD Instinct™ MI355X sports 𝟮𝟴𝟴𝗚𝗕 𝗼𝗳 𝗛𝗕𝗠𝟯𝗘, 𝟴𝗧𝗕/𝘀 𝗼𝗳 𝗽𝗲𝗮𝗸 𝗺𝗲𝗺𝗼𝗿𝘆 𝗯𝗮𝗻𝗱𝘄𝗶𝗱𝘁𝗵 𝗮𝗻𝗱 𝟳𝟴.𝟲 𝗧𝗙𝗟𝗢𝗣𝘀 𝗼𝗳 𝗽𝗲𝗮𝗸 𝗙𝗣𝟲𝟰.

Put eight in a node and you have 2.3TB of HBM3E: enough to hold an entire frontier-scale model in memory on one machine. For accelerated HPC, it means bigger simulations resident on a single GPU, bandwidth-bound kernels with space to breathe, and serious double precision.

SCALE compiles supported CUDA code to run natively on it, cutting the effort required to move existing applications.

Our compiler is built to use what the hardware offers. One example: AMD GPUs can pass data between threads through DPP, hard-wired lane permutations that cost almost nothing. SCALE recognises the patterns in ordinary CUDA shuffles and maps them onto DPP automatically, so your code takes the fast path without a line of AMD-specific code.

The silicon was always capable. What held CUDA workloads back on AMD was getting the code there without leaving performance behind on the way. That is a compiler problem, and compilers can be fixed once for everyone.

We are now listed in @AMD's Instinct AI & HPC Software Ecosystem Program!
https://t.co/cMTMfyNFun

[Spectral Compute @SpectralCom]

A hybrid GPU fleet only pays off if every part of it runs your code fast.

The best price-performance moves between vendors and hardware generations. Mixing accelerators is how you follow it.

The catch is the software. A second vendor usually means a second codebase, tuned to the same standard as the first. Every optimisation lands twice. Every release is validated twice. The engineering bill eats the hardware savings.

https://t.co/xaoRxAEauZ removes that step. Your existing CUDA code compiles natively for AMD and NVIDIA GPUs, and the compiler does the tuning: novel optimisations that use each target's own hardware features, including ones that cannot be expressed in source at all.

On the Extended OpenDwarfs suite, unmodified CUDA code compiled with SCALE 1.7.3 is 𝗼𝗻 𝗽𝗮𝗿 𝘄𝗶𝘁𝗵 𝗛𝗜𝗣 𝗮𝗻𝗱 𝗻𝘃𝗰𝗰 𝗼𝗻 𝗮𝘃𝗲𝗿𝗮𝗴𝗲, and faster on about half the workloads (AMD MI300X and NVIDIA B300, September 2026).

𝗢𝗻𝗲 𝗰𝗼𝗱𝗲𝗯𝗮𝘀𝗲. 𝗘𝘃𝗲𝗿𝘆 𝗮𝗰𝗰𝗲𝗹𝗲𝗿𝗮𝘁𝗼𝗿 𝗶𝗻 𝘁𝗵𝗲 𝗳𝗹𝗲𝗲𝘁 𝗲𝗮𝗿𝗻𝗶𝗻𝗴 𝗶𝘁𝘀 𝗸𝗲𝗲𝗽.

Benchmarks: https://t.co/rCpTBKylET

[Spectral Compute @SpectralCom]

Read the paper: https://t.co/A0ANUBlQoy
See the benchmarks: https://t.co/BgFDwm1x8o

[Spectral Compute @SpectralCom]

The fairest way to compare GPU toolchains is to hand them the same workload.

That is the idea behind Extended OpenDwarfs, the benchmark suite built by our colleague Beau Johnston: 16 benchmarks spanning 13 Berkeley dwarfs, each written in CUDA, HIP and OpenCL, with every run checked for correctness.

Beau has now turned it on https://t.co/xaoRxAEauZ. The CUDA code is compiled with SCALE and measured against native HIP on AMD and nvcc on NVIDIA, on systems from AMD Vega to NVIDIA Blackwell.

The result is a peer-reviewed paper, 𝘚𝘤𝘢𝘭𝘪𝘯𝘨 𝘵𝘩𝘦 𝘌𝘹𝘵𝘦𝘯𝘥𝘦𝘥 𝘖𝘱𝘦𝘯𝘋𝘸𝘢𝘳𝘧𝘴, which Beau presented in Singapore at the NVIDIA Supercomputing User Group (NVSUG) workshop at ICPP '26. Code and raw data are open, so anyone can rerun it.

The same suite runs our newest benchmarks too: with SCALE 1.7.3, unmodified CUDA code is 𝗼𝗻 𝗽𝗮𝗿 𝘄𝗶𝘁𝗵 𝗛𝗜𝗣 𝗮𝗻𝗱 𝗻𝘃𝗰𝗰 𝗼𝗻 𝗮𝘃𝗲𝗿𝗮𝗴𝗲, and faster on about half the workloads.

[Spectral Compute @SpectralCom]

You shouldn't have to pick a GPU vendor up front. And your codebase shouldn't pick one for you.

That was our CEO @SpectralMichael's point on stage at the The Xcelerated Compute Show in London, in a fireside chat with @dcdnews's Vlad - Gabriel Anghel.

He calls it team rainbow 🌈: rather than signing up with team green, red or blue, you mix and match.

He compared the CUDA ecosystem to the UK plug: you can argue it's the better socket, but nobody rips out the wiring to switch. And rewriting code for each vendor is a maintenance bill that grows with every vendor you add.

So keep your CUDA code. https://t.co/xaoRxAEauZ compiles it for NVIDIA and AMD GPUs. You get more performance per dollar from the hardware you already own, and you buy your next GPU because it's the best one for the workload, not because it's the only one your code runs on.

@BerryWrites wrote it up for @sdxcentral: https://t.co/97ZM6z0Coa

[Spectral Compute @SpectralCom]

The hardest test for a CUDA compiler is code that was never written with it in mind.

So on top of our own tests, we build 48 open-source CUDA projects - FFmpeg, OpenCV, GROMACS, hashcat and more. We follow each project's own build instructions as closely as we can, then run its own test suite on AMD and NVIDIA GPUs.

That is a deliberately unforgiving test, and it steers our roadmap. API coverage is driven by what real projects actually reach for, discovered by watching real builds fail - not by working alphabetically through a specification.

The scripts and the results for each release are public, failures included. Read them and pick holes in them - repo link: https://t.co/kZKxbLAuqX

𝗔 𝗰𝗼𝗺𝗽𝗶𝗹𝗲𝗿 𝘁𝗵𝗮𝘁 𝗼𝗻𝗹𝘆 𝗰𝗼𝗺𝗽𝗶𝗹𝗲𝘀 𝘁𝗵𝗲 𝗲𝘅𝗮𝗺𝗽𝗹𝗲𝘀 𝗶𝗻 𝗶𝘁𝘀 𝗼𝘄𝗻 𝗱𝗼𝗰𝘂𝗺𝗲𝗻𝘁𝗮𝘁𝗶𝗼𝗻 𝗶𝘀 𝗮 𝗱𝗲𝗺𝗼.

Come tell us what to test: https://t.co/feLXhJnwSb

[Spectral Compute @SpectralCom]

𝗦𝗖𝗔𝗟𝗘 𝟭.𝟳.𝟯 𝗶𝘀 𝗼𝘂𝘁.

This release adds a Rocky Linux / RHEL 8 package, and supports older glibc in general.

More of the compiler now ships statically linked, so it is less likely to clash with other LLVM-based compilers.

Texture API support expands substantially. And there is the usual long list of nvcc-compatibility, runtime and CUDA-X library fixes.

Grab the new release from https://t.co/xaoRxAEauZ.

𝗗𝗿𝗼𝗽-𝗶𝗻 𝘀𝗵𝗼𝘂𝗹𝗱 𝗰𝗼𝘃𝗲𝗿 𝘁𝗵𝗲 𝘀𝘆𝘀𝘁𝗲𝗺 𝗮𝘀 𝘄𝗲𝗹𝗹 𝗮𝘀 𝘁𝗵𝗲 𝗰𝗼𝗱𝗲.

Full release notes: https://t.co/BKod4cjhgh

[Spectral Compute @SpectralCom]

@ToniRMCardoso Thanks for the retweet! 🚀

[okimraise.eth @ok1mraise]

@SpectralCom llama.cpp carrying a hip tree that trails cuda is the quiet tax. cutlass having no amd door at all is the sharper split

[Spectral Compute @SpectralCom]

There are two kinds of well-known CUDA project.

The first kind ships two codebases: a CUDA one and a hand-written HIP port. Hashcat, GROMACS, Cycles, llama.cpp all carry both. Every change has to land twice, and the port usually trails the original.

The second kind has no working AMD route at all. CUTLASS, AMGX and others simply do not run on AMD hardware - unless you compile them with https://t.co/xaoRxAEauZ.

For the first group we are a way to delete a codebase. For the second we are the only door in.

Best part? SCALE is free for non-commercial use. Try it against your codebase, and drop into our Discord to let us know how it fared!

https://t.co/00sLrKORHm

[Spectral Compute @SpectralCom]

Join our Discord: https://t.co/sWKIICCvaj

[Spectral Compute @SpectralCom]

"Portable code is slower than hand-tuned code" is one of those things everyone knows and nobody rechecks.

CPU compilers disproved it decades ago. They exploit diverse hardware features better than most people manage by hand.

The GPU version of that argument is very concrete. Moving data between lanes can go through a general permute instruction, which bounces the data off the shared memory cache at roughly ten times the cost of a register move. Or it can go through a hardwired permutation pattern that is 𝗹𝗶𝘁𝗲𝗿𝗮𝗹𝗹𝘆 𝘄𝗶𝗿𝗲𝘀 - close to free, and expressed as a flag on an operand rather than an instruction of its own.

The catch is that the available patterns change between hardware generations, so almost nobody reaches for them by hand.

A compiler can. https://t.co/xaoRxAEauZ takes a whole reduction loop, works out what is actually being computed across which lanes, and rebuilds it from the cheap patterns - chaining two of them where no single one matches.

The same analysis then found something on NVIDIA hardware: a whole-warp reduction instruction most people never write the metaprogramming to reach. SCALE now uses it automatically wherever it applies.

Read our blog post "Optimizing CUDA Shuffles with SCALE": https://t.co/JossDaRfwY

[Spectral Compute @SpectralCom]

𝗡𝗼𝘁 𝗲𝘃𝗲𝗿𝘆 𝗸𝗲𝗿𝗻𝗲𝗹 𝗴𝗲𝘁𝘀 𝗮 𝟭𝟬𝟬𝘅.

A Monte Carlo run splits into millions of independent jobs. GPUs eat that. Hundreds of times a CPU core, easily.

An FDTD stencil is limited by memory bandwidth, not arithmetic. It runs as fast as the memory allows and no faster.

A sparse implicit solve is the awkward one. On the open-source OPM Flow reservoir simulator, a published comparison[1] put one GPU at about 5.6x a dual-threaded MPI process.

All three get sold as "GPU accelerated".

So when someone quotes you a speed-up, ask which kernel it came from. Borrowed from another shape, it tells you nothing about yours.

Ours, same treatment: on Rodinia, against hand-written HIP ports on an MI300X, https://t.co/xaoRxAEIkx averaged 𝟲.𝟭𝟵𝘅. Up to 33.8x. Faster on 10 of the 14.

Benchmarks: https://t.co/ijOXwyH47y

[Spectral Compute @SpectralCom]

Most real CUDA codebases have inline assembly in them somewhere.

Automated porting gives up on it. There is no source-level translation of inline PTX, so the code someone wrote specifically to be fast is the code that does not come across.

https://t.co/xaoRxAEauZ parses it instead. Inline PTX is raised into the compiler's own intermediate representation, optimised like any other code, then lowered back onto whatever instructions the target hardware actually has.

A three-input bitwise operation written as inline assembly comes out the other side as two native AMD instructions, because once it is real code the optimiser can fold it.

This pays off on NVIDIA hardware too. Plenty of inline PTX in the wild was written around toolchain limitations that no longer exist, and assembly a compiler cannot read blocks it from optimising everything around it.

𝗣𝗼𝗿𝘁𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝘀𝗵𝗼𝘂𝗹𝗱𝗻'𝘁 𝗰𝗼𝘀𝘁 𝘆𝗼𝘂 𝘀𝗽𝗲𝗲𝗱.

[Spectral Compute @SpectralCom]

𝗖𝗼𝗺𝗽𝘂𝘁𝗲 𝗮𝘃𝗮𝗶𝗹𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗶𝘀 𝗮 𝗯𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸.

New accelerators reach a handful of clouds first, and capacity stays tight for a while after that. If your code only builds for one vendor, you're stuck waiting on that vendor's capacity.

https://t.co/xaoRxAEIkx compiles accelerated HPC codebases to run natively on both AMD and NVIDIA GPUs. That widens the pool of capacity you can actually use.

𝗣𝗿𝗶𝗰𝗲 𝗶𝘀 𝗼𝗻𝗲 𝗯𝗲𝗻𝗲𝗳𝗶𝘁. 𝗚𝗲𝘁𝘁𝗶𝗻𝗴 𝗰𝗼𝗺𝗽𝘂𝘁𝗲 𝘄𝗵𝗲𝗻 𝘆𝗼𝘂 𝗻𝗲𝗲𝗱 𝗶𝘁 𝗶𝘀 𝘁𝗵𝗲 𝗯𝗶𝗴𝗴𝗲𝗿 𝗼𝗻𝗲.