VUnit

[VUnit @VUnitFramework]

...

[VUnit @VUnitFramework]

Let's see if we can have a LinkedIn survey with any statistical significance

https://t.co/MYQrqPtnUk

[VUnit @VUnitFramework]

Open Source Tools for Mission Critical Hardware Verification https://t.co/1i6jPKT0sg

#vhdl #systemverilog #semieda #opensource #fpga #asic #verification #vunit

[VUnit @VUnitFramework]

#FPGA #ASIC #VHDL #semieda #verification #UVM #openscience

https://t.co/CjIJ2FjdLg

[VUnit @VUnitFramework]

Continuous Integration with 10 lines of code. VUnit Action in action.

https://t.co/75cchGVjnB

#continuousintegration #VUnit #FPGA #ASIC #verification #VHDL #semieda #githubactions

[VUnit @VUnitFramework]

What Can GitHub Tell Us About the HDL Industry? Part 2 https://t.co/uxgB26JcvS

#FPGA #ASIC #verification #semieda #VHDL #openscience

[VUnit @VUnitFramework]

"Combining GHDL + VUnit (which includes OSVVM) + VHPIDIRECT (VHDL 2008) is a very powerful environment"

Hardware Description Language (HDL) abstraction - VHDL - Systemverilog
https://t.co/OqUHVAYxd5

#FPGA #ASIC #semieda #VHDL #SystemVerilog

[VUnit @VUnitFramework]

#semieda #ASIC #FPGA #VHDL #SystemVerilog #verification

[VUnit @VUnitFramework]

For years our users have requested **full** #VUnit support for @XilinxInc XSIM simulator. A minor update to XSIM that gives VUnit users extra licenses when running automated test runs. It's now the top discussion at (https://t.co/XVfGAfnCIs). Support that if interested. #semieda

[VUnit @VUnitFramework]

https://t.co/SLgNHBPtBz

[VUnit @VUnitFramework]

#semieda #vhdl #systemverilog #fpga #asic

[VUnit @VUnitFramework]

Dealing with legacy code and avoiding legacy code.

#semieda #vhdl #systemverilog #fpga #asic #vunit

[Tudor Timi @TudorTimi]

Am I the only one that dreads having to work in legacy project?

[VUnit @VUnitFramework]

Yes, the training can be done online. The key is not where we are but the company focused content of the training. We start with your current way of working, VUnit-based or not, and take the next most value-adding steps.

[VUnit @VUnitFramework]

I don't do scheduled #VUnit courses but I do give on-site trainings on demand. One day tailored for the company needs rather than 3 days targeting a broader audience. Last week I trained 3 teams at @saab. Contact me if you're interested. #fpga #asic #vhdl #systemverilog #semieda

[VUnit @VUnitFramework]

@Sigasi continues to add more features to their #VUnit support.

#VHDL #SystemVerilog #FPGA #ASIC #semieda

[Sigasi @Sigasi]

We have just released Sigasi Studio 4.6 with a faster new (System)Verilog preprocessor, improved graphics, bug fixes and much more. Read the full release notes: https://t.co/MGxPMb5dcd

[VUnit @VUnitFramework]

While you can discuss this anywhere it's probably most productive in our user forum https://t.co/P4YdfLne3e

[VUnit @VUnitFramework]

Many public discussions on #semieda tools capabilities are limited by what licenses allow you to say. With #VUnit you're allowed to discuss anything. Features, performance, bugs, pros/cons when compared to other tools, code quality, support etc. In fact, we want you to do that

[VUnit @VUnitFramework]

This is how we improve.
#vhdl #systemverilog #fpga #asic #openscience