VirginCMOS

#RTLDesign | #FPGAs #ASICs #SoC | #Verilog #VHDL | #C #Python | #AssemblyLanguage

[Roja Raja @RojaRaja403095]

காலை வணக்கம் உறவுகளே 💋

[VirginCMOS @VirginCMOS]

@zipcpu The Scottish vs English slang issue. In reality, big-endian vs little-endian is a much bigger ,almost like two different languages. But I just wanted to mention a simple Scottish vs English analogy.

[Zip CPU @zipcpu]

Here's a bug from this weekend: In this case, two bugs canceled each other out, leaving me believing the design worked in a configuration that I'd never hardware tested it in.

Also, a good question, how good should a "self-checking" test bench be?

You can read more about this bug here: https://t.co/oVtMF0xTnA

[VirginCMOS @VirginCMOS]

@furan My bad. What I meant is that I’ve never tried boundary scan. I’ve done normal UART debugging, but I have no idea how one would discover components on a board through JTAG debugging.
N.B: LLM can guide. Just trying to find what people used before LLM to learn that.

[Ian Hanschen @furan]

probe_passive now supports pinfiles for grabbing the current state of named pins over JTAG.

[Ian Hanschen @furan]

more of the 3D pipeline online

[VirginCMOS @VirginCMOS]

At this point New Zealand should be given to Indians. They will live there. I don't claim they make it prosperous or good. But it will be inhabitated.

[VirginCMOS @VirginCMOS]

@always_ff_rohan In an indirect way I meant the same. Instead of dieshot i thought to write stolen dieshot. Actually intellectual properties are not private any more. Steal/develop the IPs, no one care if your country has nukes and not afraid of the US. The actual blocker is lithographic tech.

[Andrew Elbert Wilson @FPGA_Zealot]

I think the $4 Shirke-lite (RP2040+ForgeFPGA) dev board could become a surprisingly capable FOSS JTAG endpoint for OpenOCD, OpenFPGALoader, and maybe even vendor tools.

[VirginCMOS @VirginCMOS]

@FPGA_Zealot Seeing JTAG on this stuff for the first time. Anychance to post a short video?

[VirginCMOS @VirginCMOS]

@ATaylorFPGA Why choose RPI over STM32 controllers? The ethernet PMOD uses an SPI interface?

[Adam Taylor @ATaylorFPGA]

Looks like the HDMI Rx and Tx Pmods are working

[Adam Taylor @ATaylorFPGA]

https://t.co/MCvXGJjfeu

[VirginCMOS @VirginCMOS]

@furan Group created? Pls add me too

[Zip CPU @zipcpu]

Feel free to join the discussion of what makes an ideal memory controller on Reddit.

https://t.co/ilvCJVy56s

[VirginCMOS @VirginCMOS]

@ATaylorFPGA Thanks for the blog, Adam! I haven’t had a chance to check the full implementation yet, but is there any chance you could share the Python code used here?

[Adam Taylor @ATaylorFPGA]

This week, I created a fun RTL project which reads data from accelerometer, gyroscope, temperature and pressure sensors. All the RTL is provided if you want to work with these sensors in other projects.

https://t.co/DnxZpIqZDC

[Zip CPU @zipcpu]

Well, let's think about that. What would constitute a "truly ideal memory controller IP"? Here are my thoughts. Let me know if I missed anything.