Alexandru Moraru

Systems Engineer · AI/ML · C/C++ · Python · Rust · CUDA · Vulkan · Compilers · Runtimes · Emulation · FPGA/ASIC · Deterministic Computing · Open Source

[Alexandru Moraru @_0xCAFEBABE]

Following up on HX89. Testing is done. Now it is documentation time.
Before the source lands, I want to be precise about what it proves and what it does not. Everything below is sorted into three tiers, and the sorting is the point.
Proved (theorems).
1Exact microscopic reciprocity of the chiral hex gas. The collision dressed PT reversor Θ = C₋PV satisfies Θ² = I and ΘFΘ = F⁻¹, giving an exact all time echo ΘFᵗΘFᵗ = I on every finite periodic axial torus. Machine certified exhaustively over all 2²⁴ states of the 2×2 torus, plus independent Python checks on larger tori. Rank three one body invariants (mass and two momenta) proved by exact rational elimination.
2A transport circle defect identity. For the isotropic 2D shear doublet, C6 symmetry forces the renormalized kernel into the form M = aI + bJ with J² = −I (Schur). Writing the complex response as Z = η + iη_H = A/(a + ib), the circle defect is exactly
|Z|² − (A/a) Re Z = A²(a − a) / (a*(a² + b²)).
Consequence: reactive/odd renormalization b(p) cannot break the circle. Only dissipative drift of a(p) can.
3Equivalence. For the parity symmetric circle anchored at the achiral point, the circle holds if and only if a(p) is constant. No third class exists inside the aI + bJ family.
Not proved (conjecture, stated explicitly).
Whether a(p) is constant in physically relevant chiral fluids. C6 alone does not force it. A Ward identity interpretation would require additional structure, such as a conservation law, a hidden symmetry, or a vanishing anomalous dimension, that C6 does not supply. The release states the RG invariance criterion that any such upgrade would have to satisfy. This is the open problem, precisely specified.

[Alexandru Moraru @_0xCAFEBABE]

🚀 Imagine a bare metal execution engine that models physical mechanics not in 2D or 3D but across a 5 Dimensional phase space.
This framework scales performance to the microsecond level by combining a deterministic 5D Lattice Gas Automaton with a custom low overhead runtime. The core architecture processes a custom Quinary Squared field with 25 unique phase states per cell. It tracks high dimensional paths and outputs the data through two native formats: raw uncompressed grayscale matrix arrays for spatial density mapping, and multi channel color vector blocks for live velocity tracking.
By mapping these high dimensional physical states directly to low level audio synthesis arrays, it enables developers to hear the structural evolution and thermodynamic entropy of a complex physical simulation in real time. Because the system operates directly on raw machine instructions with dedicated bare metal routines, it completely eliminates operating system scheduler jitter and latency overhead.
Here is how this high dimensional fluid and acoustic modeling engine can be interesting:
🔬 Computational Fluid Dynamics and Microfluidics
The engine utilizes optimized hexagonal state adjacency mapping to handle fluid equations. This makes it an ideal, lightweight alternative for modeling isotropic fluid flow, mass transport, and molecular gas diffusion in constrained environments like lab on a chip medical devices or high precision aerospace components without needing heavy cloud supercomputers.
🎵 Physical Modeling Synthesis and Wave Mechanics
By binding local kinetic energy and state matrices directly to low level pulse code modulation streams, the engine acts as a live waveguide simulator. It transforms physical boundaries into mathematical resonance coefficients, allowing researchers to accurately synthesize organic acoustic environments, material impacts, and complex sonic waveguides.
📡 Telemetry, Digital Signal Processing and Modem Design
The pipeline features automated telemetry verification loops, assessing signal degradation and tracking data payloads through custom audio sweep modulations like Frequency Shift Keying. It offers deep analytical capabilities for designing low power acoustic transmission networks and optimizing underwater or analog communication channels in extreme environments.
⚙️ Hardware in the Loop Simulation and Edge Computing
When physical systems require deterministic responses, timing accuracy is everything. This module translates intermediate representation instructions into optimized, transient machine code blocks that execute with absolute microsecond predictability, creating a highly valuable blueprint for advanced scientific edge processing devices.
This complete experimental stack is moving toward an open source release soon. If you work in complex fluid simulation, high dimensional wave geometry, or systems programming, let us connect to discuss how high dimensional automata can bridge physical states and signal processing.

[Alexandru Moraru @_0xCAFEBABE]

I’ve posted a bit about DATS already, but here’s a more detailed look at what it is, how it executes, and what I’ve now tested on real FPGA silicon.

DATS is an experimental non Von Neumann execution architecture.

It does not follow the conventional:

fetch → decode → execute → increment program counter → repeat

There is no native program counter, no instruction pointer driving progression, no implicit fall through, and no conventional instruction fetch loop.

Instead, computation is structural.

A node becomes eligible when its predecessor relations have been committed. Compatible eligible nodes can advance together in the same execution wave, then commit successor state.

predecessor state → eligibility → compatible wave → atomic commit → successor state

The current FPGA microfabric is intentionally small:

C0 → (C1 || C2) → C3

C1 and C2 become eligible together after C0 commits, so they can advance in parallel instead of being serialized as instruction 1, instruction 2.

DATS uses:

🔺 3 state rails: negative, neutral, positive
🔗 3 relation rails
🧩 4 witness classes
🌊 Dependency driven execution waves
📌 Explicit committed node state
⚠️ Observable conflict and unresolved states

A normal valid transaction completes in 3 waves:

Wave 1: C0
Wave 2: C1 + C2
Wave 3: C3

That is 4 node commits across 3 dependency frontiers.

The FPGA implementation still uses a physical clock because the fabric is synchronous digital hardware, but the clock does not define DATS semantics. The architecture decides what becomes eligible and what can commit together.

This is now beyond simulation.

Current Tang Nano 20K work includes:

🧠 369 MHz configured native target physically run
🖥️ 180 MHz native DATS + HDMI image
📈 410.510 MHz native static timing Fmax on the selected HDMI route
🎞️ 1280×720 ~60 Hz physical HDMI output
⏱️ 74.25 MHz pixel clock
🚀 371.25 MHz serializer clock
🔌 PLL lock and clock ratio monitoring
💾 SRAM configuration testing
💾 Persistent configuration and cold boot recovery verified
📺 Real monitor lock and live status output

The native carrier also tests:

Neutral → valid neutral, 3 waves
Negative → valid negative, 3 waves
Positive → valid positive, 3 waves
Dual rail → unresolved, 1 wave

The hardware tracks wave count, committed nodes, valid output, conflict state and unresolved state, with dedicated self test and fault latching.

The important part for me is not simply getting an FPGA to blink.

DATS has crossed:

architecture → RTL → synthesis → place and route → bitstream → physical FPGA → persistent boot → live HDMI

There is still much more to build, but DATS is no longer only an architectural model.

It is running on real silicon.

0xCAFEBABE

#FPGA #ComputerArchitecture #DigitalDesign #RTL #NonVonNeumann #ParallelComputing #EmbeddedSystems

[Alexandru Moraru @_0xCAFEBABE]

@niqudrift Looks interesting? Making a new ahitecture

[Alexandru Moraru @_0xCAFEBABE]

A few people will see “DATS 1.8.4” and reasonably ask: what exactly is DATS?

Short version:

It is an experimental non Von Neumann execution architecture built around dependencies, state relations and wave commits rather than a conventional instruction stream.

A normal CPU roughly follows:

fetch → decode → execute → advance PC → repeat

DATS does not make that its native execution model.

No native program counter.
No instruction pointer driving progression.
No implicit fall through.
No conventional fetch decode loop.

Instead, computation is represented structurally.

Work becomes eligible when its required predecessor relations exist.

Compatible work can advance in the same wave.

A completed wave publishes a successor state.

Progress comes from the dependency graph, not from “execute instruction N, then N+1.”

The native state model is also different.

DATS uses three explicit state rails:

negative
neutral
positive

Alongside state, the machine carries relation and witness information.

Conflict and unresolved conditions stay visible instead of being silently collapsed into a normal value.

The current FPGA microfabric is intentionally small: 4 execution nodes.

That is enough to physically test the important part:

one node can feed two independent nodes, those nodes can become eligible together, and their results can converge into another node through compatible wave execution.

Committed state is treated as committed history.

A later transition creates a successor rather than pretending the previous state never existed.

That matters when building deterministic systems where the machine should be able to explain how it got somewhere.

And this is no longer only a software model.

The current DATS carrier has now been exercised on a physical Tang Nano 20K FPGA:

⚡ 369 MHz configured native target physically run
🖥 180 MHz native + HDMI build
📈 410.510 MHz routed native Fmax on that HDMI image

There is still a much larger system being built above this substrate.

I am not calling that finished.

For now the interesting result is simpler:

DATS has crossed from architecture → RTL → place & route → bitstream → real silicon.

Build close to the machine. Measure what actually runs.

0xC0FFEEBABE

[Alexandru Moraru @_0xCAFEBABE]

⚡ DATS 1.8.4 is now running on real FPGA silicon.

I have the current carrier running on a physical Tang Nano 20K, with the execution fabric, clocking, persistent recovery and HDMI path exercised on hardware.

🧠 369 MHz configured native target physically run
🖥️ 180 MHz native clock in the HDMI integrated image
📈 410.510 MHz native static Fmax reported for the selected HDMI route
🎞️ 1280 × 720 at ~60 Hz
⏱️ 74.25 MHz pixel clock
🚀 371.25 MHz serializer clock

The current native microfabric has 4 execution nodes, with dependency driven wave execution and compatible commits rather than a conventional program counter based instruction stream.

At the hardware level the current carrier includes:

⚙️ ALU and LUT mapped compute logic
💾 Flip flop registers for retained state, counters and control state
🌊 4 node native microfabric
🔺 3 state rails
🔗 3 relation rails
🧩 4 witness classes
📊 Wave counter and committed node visibility
⚠️ Conflict and unresolved state visibility
🔌 2 PLL clock domains
➗ 1 hardware clock divider
📡 3 OSER10 TMDS serializer modules
🔷 4 differential HDMI output channels
💾 Onboard SPI flash for persistent configuration
🧪 Dedicated control and self test logic

Cold boot recovery is verified, the SRAM qualification image loaded successfully, and the HDMI monitor locked to the physical output.

The larger system is still being built, so I am keeping the claim where the evidence is today.

Real board. Real clocks. Real mapped logic. Real state registers. Real HDMI. Real silicon execution. ⚡

#FPGA #HardwareEngineering #DigitalDesign #ComputerArchitecture #RTL #Verilog #EmbeddedSystems #Silicon #ElectronicsEngineering #Engineering

[Alexandru Moraru @_0xCAFEBABE]

@arexobcd https://t.co/asnXml2ugU

are you sure about that?

[Alexandru Moraru @_0xCAFEBABE]

@DarrelFrater https://t.co/asnXml2ugU

Have fun

[Alexandru Moraru @_0xCAFEBABE]

@lightsilver323 https://t.co/hQaD22f5vk

https://t.co/asnXml2ugU

[Alexandru Moraru @_0xCAFEBABE]

I’m starting this account as a place to share the engineering work I build and open-source.

My work spans systems programming, deterministic computing, AI/ML, compilers, runtimes, scientific computing, GPU/graphics, emulation and low-level software.

15 public repositories so far:

https://t.co/wAOkmE5oWy

↓ SYSTEMS & DETERMINISTIC COMPUTING

deterministic_neuro_route_C
Portable C11 neural-inspired deterministic graph routing with 256-bit Hamming-distance spatial matching.

neuro_routingC_DevTools
Developer tooling around the routing engine for project detection, builds, tests and execution.

-deterministic-lead-processor
Portable deterministic lead-processing engine combining business logic with OpenAI-compatible LLM workflows.

ClientOpsCRM-Deterministic-Local-First-CRM
Deterministic local-first CRM architecture with relational persistence and operational tooling.

↓ LANGUAGES, COMPILERS & RUNTIMES

LLRLANG
A self-hosting native language/compiler project focused on deterministic compilation and auditable bootstrap paths.

BitWeave
Human-readable binary-oriented source → canonical bit representation → native executable output.

cocytus
An esoteric deterministic language/runtime built around exact arithmetic, reversible transformations, bounded execution and deliberately hostile execution semantics.

↓ COMPUTATIONAL RESEARCH

AM-ASG8-Activation-State-Geometry-Benchmark
Exhaustive analysis of all 256 states of an 8-bit Boolean activation space with independent verification and visualization.

DACB
Deterministic Affine Chain Benchmark for reproducible arithmetic and implementation comparison.

benchmark_suite
Reproducible mathematical workloads built around exact operations and independently verifiable results.

↓ SCIENTIFIC COMPUTING

deterministic_2d_wave_equation_C
Portable C11 2D wave-equation solver using explicit finite differences, leapfrog integration and periodic boundaries.

D_2d_wave_equation_solver
Deterministic Python implementation of the same numerical problem.

Fluid-logic-test
D2Q9 Lattice Boltzmann fluid simulation used for deterministic computational experiments.

↓ DEXR

dexr-research-thesis
Research and reproducibility material around deterministic visual computing and runtime architecture.

Dexr-Professional-Manual
Technical documentation and engineering reference material for the DEXR ecosystem.

The common theme across most of my work:

Build close to the machine.
Make behavior reproducible.
Keep the implementation inspectable.
Measure what actually runs.

C · C++ · Python · Rust · CUDA · Vulkan · AI/ML · Compilers · Runtimes · FPGA/ASIC · Scientific Computing · Deterministic Systems

More work going public as it becomes ready.

0xC0FFEEBABE → BUILD → TEST → BREAK → FIX → REPEAT

[Alexandru Moraru @_0xCAFEBABE]

@uffyebanda True dat

[Alexandru Moraru @_0xCAFEBABE]

@elonmusk @elonmusk Mf you are multi onaire. You have good cars good house and top pussy.And yet you find it normal to come and vomit all your mental issues https://t.co/LGoQeEvvai are not the clown you are the whole circus

[Alexandru Moraru @_0xCAFEBABE]

@VoteHarrisOut Get some https://t.co/bvru5MmHoY became edge lords to the rest of the https://t.co/wSRLq71Zbq's cringe

[Alexandru Moraru @_0xCAFEBABE]

@PlayConcord This aged so well.Cheers next time make an acutally good game