From @UWMadisonECE, #BitSAD enables simulation and hardware generation of general purpose #bitstream computing circuits (w/ population coding support for parallelization) -@darsnack https://t.co/iESH0AB2Wk
Researchers at @LehighU design a #framework based on #LLVM#compiler to support #TM in #C++ by forbidding explicit #self-abort, and by introducing an #executor-based mechanism for running transactions.- Pantea Zardoshti
https://t.co/04lTMW71qC
Research @iitmadras#iitm PACE lab #optimizes remote communication (by a large factor) for PGAS based #parallel programming languages using #program analysis and transformation techniques. @KrishnaNandiva @iitmcse@acmtaco: https://t.co/JP0xWZbslg
@CAL_NTNU researchers show that pre-computing iterative stencil loop coefficients across multiple iterations at design time enables #FPGA-based #accelerators that have 7.7X higher throughput than the current state-of-the-art. https://t.co/wp8qAJMscv
A #hardware-based high-frequency checkpointing mechanism is explored to achieve efficient #inmemory data persistence on #NVM - Song Wu, https://t.co/BWjoymVec8
Researchers at #NEU demonstrate a highly effective and light-weight technique to exploit data block cooperation that advances error correction capability of #NVM. https://t.co/KyjktORm9E
"#Compiler#optimization can reach the #performance of optimized #BLAS libraries without the need for an external implementation or automatic tuning - Roman Gareev, Tobias Grosser, and Michael Kruse #LLVM" https://t.co/oVODGUmevu
Research @tcd#SCSS#stglab shows #PASM saves 54% ASIC power & 64% FPGA power with only 12% latency increase in CNN MACs @jpgarland@acmtaco https://t.co/M1RcWTPCGU
#Benzene efficiently utilizes distributed SRAM/STT-RAM hybrid #cache to achieve 47% reduction in its energy consumption. - Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sanchez, Donghoon Yoo, and Soojung Ryu
https://t.co/wwAonXYCbl
Adaptive Turbo Boost (ATB): Adaptively using Decoupled Look-Ahead(DLA) as a boosting strategy for improving #performance and #energy efficiency of conventional
#turboboost. - Kondguli and Huang. https://t.co/AcWs6X8jO4
#HAShCache is the first work to use heterogeneity-aware mechanisms to manage the die stacked DRAM as cache to improve performance of integrated CPU+GPGPU processors over SOTA #HPC#microarchitecture@IIScCSA@adarsh_patil https://t.co/cgbxcYXDhO
#HAShCache shows that using a die stacked DRAM as cache for integrated heterogeneous CPU+GPGPU processors results in 200% performance improvement in overall system performance @IIScCSA@adarsh_patil#HPC#microarchitecture https://t.co/1pcB4eXEc3