Huawei Publishes V2 of "Tao's Law" Paper, Laying Out a New Path for the Post-Moore Era
On July 3, Huawei’s He Tingbo officially released Version 2 of the paper "A Time-Scale Miniaturization Theory for Multi-Level Electronic Systems" on the ChinaXiv platform. This update moves the theory from an initial concept to a closed-loop framework backed by real engineering data — offering a homegrown, top-level theoretical foundation for the semiconductor industry beyond Moore’s Law.
Compared to the V1 release in May, the new version expands into a full eight-chapter academic structure, adding practical engineering details such as the LogicFolding fold ratio model, unit-level optimization for 3D hybrid bonding, and a unified interconnect bus architecture. It breaks through the traditional limitation of 3D stacking, which previously only worked at the macro-block level.
For the first time, the paper includes production test data from the Kirin 2026 series, with head-to-head comparisons against previous flagship chips. Using concrete metrics like voltage, frequency, power density, and die area, it demonstrates real-world performance gains from the time-scale miniaturization paradigm.
Rather than following Moore’s Law’s single-minded focus on geometric scaling, Tao’s Law centers on a system-level metric — the time constant τ — to reduce signal transmission delays across devices, circuits, chips, and entire systems. The result: steady gains in computing density without relying on extreme ultraviolet lithography or ever-shrinking process nodes.
This marks a milestone for China’s semiconductor industry — proposing a globally applicable new roadmap for industry evolution, on its own terms.
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