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ChipForge New Challenge is Live: This Time Complete Pipelined RV32IMC core
We’ve entered the next phase at ChipForge — Challenge_0007 focuses on implementing the M (Multiply/Divide) and C (Compressed Instructions) extensions for our pipelined RV32I core.
Why We Started with RV32I
Before building AI-specific hardware — our ultimate goal — we first needed a fully functional general-purpose processor.
The RV32I ISA provides all the fundamental arithmetic, logic, and control instructions needed to execute any algorithm. However, it lacks hardware multiplication and division.
In RV32I, these operations are done in software (using shift-and-add/subtract), which works correctly but is slow — often taking up to 32 iterations.
This makes RV32I a complete yet performance-limited baseline — an ideal foundation for further hardware acceleration.
Extension Goals
- M Extension (Multiply/Divide):
Adds dedicated hardware for multiplication and division, cutting multi-cycle software operations down to just a few hardware cycles — drastically improving speed and efficiency.
- C Extension (Compressed Instructions):
Introduces 16-bit instruction encoding, allowing ~70% of instructions to be compressed. This reduces overall program size by 30–50%, enhancing code density and improving cache and memory efficiency.
What This Means
Together, these extensions move our processor closer to real-world embedded and edge AI workloads — combining compact design with improved performance and energy efficiency.
Summary
The RV32I baseline challenge was our first major step — building the core foundation.
Now, with Challenge_0007, we aim for higher speed, smaller code size, and greater efficiency through hardware multiply/divide and instruction compression.
Each milestone brings us closer to our vision:
A compact, secure, high-performance Edge AI chip purpose-built for intelligent computing at the edge.
— Team $TATSU | ChipForge (SN84)
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