@humphilomath maybe in the US. i know georgia tech started around the same time. now a lot do it, and more will do it. money from CEMiD and chips act funding a lot of programs across the country.
this will be my research profs new class. i’m helping make a lot of this.
@humphilomath for my university project team Cornell Custom Silicon Systems.
there’s an Analog-Mixed Signal implementing an 8bit SAR ADC.
Digital chip implementing an async FIFO, FFT and simple classifier, with some BIST.
RF chip implementing a 915 MHz OOK transceiver.
I didn’t know this a few years ago but the gap between like an “ok” physical design and a spectacular one is wiiiiiide as hell.
It’s the difference between hitting F_MAX at 600 MHz and 1.5 GHz on an advanced node like 65 nm. And now with so many chip startups all relying on a few design houses the gap is getting wider and wider.
Broadcom isn’t going to optimize the living shit out of your chip because the engineering hours explode to do so. If only there was a way to get good fast before the ladder is pulled up.
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