‘DARE takes the ambition for self-sufficiency in software-hardware technology to a new level’ – Osman Ünsal in #HiPEACinfo75 👉 https://t.co/jWy7yi2MVO
European technological self-sufficiency is becoming a topic of increasing importance. The chips – and their software – providing the compute muscle for high-performance, artificial intelligence applications are a key plank of technological autonomy as the AI era picks up pace.
Bringing together 38 partners from 15 different countries across Europe (with many HiPEAC members represented), @dare_euproject will develop chiplets for #HPC and #AI, designed and implemented in Europe. For #HiPEACinfo75, we caught up with DARE coordinator Osman Unsal and EU projects innovation manager Vanessa Iglesias, both @BSC_CNS, to find out what this project sets out to achieve and the impact it will have on the European technology ecosystem.
@EuroHPC_JU | @imec_int | @fzj_jsc | @AxeleraAI | @Openchip_ | @Codasip
#HiPEACinfo75 is out now! 👉 https://t.co/x1ivvNUqsP
🛠️ The theme of this issue is tools. Featuring:
🎙️ Interview with Osman Unsal and Vanessa Iglesias (@BSC_CNS ) on @dare_euproject
📈 European ecosystem updates, including @semidynamics , ZeroPoint Technologies, Daisytuner, Mosaic SoC, Openchip and TASKING
🧠 How the @smiliespolito tool Spiker+ simplifies custom hardware for spiking neural networks
⚙️ Ben van Werkhoven on KernelTuner for
#GPU applications, Luca Fanucci on FPG-AI and Marc Michalke on #JupyterHub for ML in @icos_project
🔋 Increasing datacentre performance per watt with Energy Aware Solutions' Julita Corbalán and Luigi Brochard
🌐 Using multi devices with #OpenMP
The role of SiPearl in the Arm ecosystem and @RiserProject
🛠️ Tools in the #HiPEACVision and #DiscoverUS Vision
🛡️ How researchers at @BoschResearch are securing tomorrow's vehicles, today
🗞️ How the #Karolina supercomputer is helping Bellmer optimize paper manufacturing
👥 @EARASHI2022's human-centred approach to AI-enabled workplaces
Plus how Alberto Ros's ERC sparked PhD theses, how Samuel Coward's 'acadustrial' PhD led to the best of academia and industry, and how Karthick Panner Selvam is helping predict ML performance across hardware resources.
📣The #RISCVSummitEurope is happening this week in Paris.
Our colleague, Alexandra Kourfali , Programme Manager for R&I, will discuss the #EuroHPC roadmap, the RISC-V landscape for #HPC, and more.
🔗 https://t.co/hGP9a8ZLwJ
📢 Today at #RISCVSummitEurope!
🕒 14:45 CET, T2.5.02, Gaston Berger (S2)
From Open Silicon to Sovereign Supercomputing with Alexandra Kourfali, @EuroHPC_JU 🇪🇺
📍Visit @BSC_CNS booth #27 for the new RISC-V tech catalogue!
https://t.co/Yh9W9b0BUz
#EuroHPC#RISCV#HPC
🌅 Community Breakfast @ RISC-V Summit Europe 2025
Start your Wednesday, May 14th, with good coffee and great conversation. Join us for a panel-led breakfast focused on R&D, industry insights, and what’s really happening in the RISC-V community, the wins, the gaps, and where we go next.
🕗 8:00–9:00 AM (Breakfast & doors open at 7:30 AM)
📍 Louis Armand Room
🎟️ Included with registration: https://t.co/EfO3spl740
📣@dare_euproject was launched last month to pave the way for European-led technological solutions in #HPC!
Based on #RISCV, this @EuroHPC_JU project coordinated by @BSC_CNS will deliver high-performance & energy-efficient supercomputing for R&I!
🔗 https://t.co/WQQu9evzaz
✨ 20 Years of HiPEAC celebrations on #HiPEACTV ✨ – Mateo Valero
👉https://t.co/L0meQXB71o
In the first of a series of talks celebrating the 20th anniversary of HiPEAC, Mateo Valero takes us on a journey from the beginning of HiPEAC and Barcelona Supercomputing Center to the building of a thriving #HPC research ecosystem in Europe and the opportunities opening up in artificial intelligence #AI.
Hundreds of RISC-V enthusiasts from around the world joined Hackathon Online, with in-person hubs lighting up across the globe! 🌍🎉
🎤🏆 Mark your calendar — Wednesday April 16 at 7AM PST, we’re going live to showcase the Top 10 Solutions and announce the WINNERS!!
https://t.co/EGDjKlHYe2
💬 To everyone who participated — Tell us how it went! What did you think of the challenges from Andes and Codasip?
#RISCVhackathon
If you missed the @Etp4HPC webinar "OpenCUBE & RISER: Two projects to advance European cloud platforms" featuring speakers from the OpenCUBE project and RISER, it is now available here:
🔗 https://t.co/MtATufT9mq
📣 Call for workshops: #HiPEAC26 👉 https://t.co/UPsK5N6I5D
🗓️ 26-28 January 2026 | 📌 Kraków
⏳ Deadline for submissions: 1 July 2025
Further information 👉 https://t.co/v6IE8IuN3i
@RiserProject | @DECICE_EU | @pilot_euproject | @AGH_Krakow
Calling all RISC-V researchers and universities: The RISC-V University Demo Day is back for its 2nd year at #RISCVSummitEurope! 🎓💡
This is your chance to show what you’re working on — whether through hardware prototypes, software demonstrations, or creative applications. From developing innovative RISC-V processor designs to enhancing software ecosystems for RISC-V systems or advancing RISC-V-based IoT solutions, we’re eager to see your contributions!
📅 Demo Day: May 15
⏰ Submit by: April 25
Submit your demo: https://t.co/NocLMVcsdh
📣 hashtag#HiPEAC26 Call for papers 👉 https://t.co/Xhk0m3S3af
🗓️ 26-28 January 2026 | 📌🇵🇱 Kraków, Polska
⏳ Deadline: 1 June 2025
Further information 👉 https://t.co/DqLXgOhxAz
@EU_CloudEdgeIoT | @EuroHPC_JU | @DigitalEU
RISC-V for HPC: The journey in Europe so far
👉 https://t.co/Psc4RFMsiU
As @dare_euproject kicks off this spring, it feels like an opportune moment to look back over the work achieved around #RISCV for #HPC in Europe up until now. To celebrate 20 years of HiPEAC, prior to #HiPEAC25 we spoke to Filippo Mantovani (@BSC_CNS) to learn why RISC-V has been embraced as a tool for technological self-determination, what key projects including the @EuProcessor, @pilot_euproject, @EUPEX_pilot, @eprocessor_eu and MEEP have achieved so far, and what lies ahead for the development of the RISC-V ecosystem.
@risc_v | @EuroHPC_JU