Dario Fresu

Master EMC/EMI Control in PCB Design here:

[Dario Fresu @dario_fresu]

Why Do So Many Products Fail EMC Tests?

Because the basics of EMI aren’t understood.

The first PCB I designed? I barely considered these principles.

Displacement current was just a vague term from Maxwell’s equations that didn’t mean much to me.

Return current? It wasn’t even on my radar.

With modern schematic simplifications, the return path to the signal source isn’t even drawn. I didn’t think it mattered because I assumed the current would simply "sink" into whichever GND connection I made.

I thought that if the schematic was correct, the PCB design would work too.

I’d add GND pours to all the leftover space—paying no attention to antenna-like structures.

If the current was high and I had the budget, I’d throw in a power plane—maybe even segmented into a few voltage rails—just to make sure the power was solid.

Unfortunately, this is still how many PCB designers work today.

And this is why so many products fail EMC tests.

It’s not that the solutions are overly complicated.

The real challenge is unlearning outdated practices.

We’re taught electromagnetic theory and electronics from the wrong perspective (thinking about electrons instead of fields), and these approaches no longer work with modern technology.

Here’s where it starts:
How do signals physically propagate inside a PCB?

It’s a simple question, but understanding the answer can change the way you design PCBs forever.

I’ve broken it down in this article and video:
https://t.co/nXRTfrPe0Z

– Dario

P.S. Ready to take your EMC/EMI skills to the next level?
Start with my free online course: https://t.co/y8g3Y04pVQ

[Dario Fresu @dario_fresu]

If you want to learn more about professional PCB design, join our community here: https://t.co/av3G4V6RdR

[Dario Fresu @dario_fresu]

Myth: the ground triangle is one big sink at zero volts. It isn't. The plane is copper, and copper has impedance, so two points on the same return net a few centimeters apart aren't at exactly the same voltage. The return current flows in the plane right under the trace.

[Dario Fresu @dario_fresu]

@kakuiwata I'll see you there then 👍

[Dario Fresu @dario_fresu]

Route each differential pair tightly coupled so noise lands on both lines and the receiver can reject it. Then leave room to the next pair to limit crosstalk.

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[Dario Fresu @dario_fresu]

A product that fails EMC can't go on sale, and a respin costs far more than the review. A quick review of return reference, impedance and crosstalk can find most issues in minutes.

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[Dario Fresu @dario_fresu]

@Jasper_3301 You want to maximise energy transfer, not suppres it. The issue is that energy is being converted or redirected unintentionally and where it shouldn't. Thats why even if those techniques can allow you pass some tests, they are still patches that only alleviate a deeper issue.

[Dario Fresu @dario_fresu]

Board failing EMC? Start with three checks: return reference, impedance continuity, crosstalk. In my experience they cover most failures. Cables and placement come after.

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[Dario Fresu @dario_fresu]

Digital and analog signals need an adjacent return reference plane (RRP). Some antennas, like a quarter-wave monopole, need a large conductor as their other half.

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[Dario Fresu @dario_fresu]

You don't need to solve Maxwell's equations by hand. You do need to understand what they describe, or you can't tell when a calculation is wrong.

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[Dario Fresu @dario_fresu]

A layout simulation flags discontinuities, including ones you meant, like an isolation barrier. Decide what you expect first, then judge each error case by case.

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[Dario Fresu @dario_fresu]

Reviewing a layout? Think in the frequency domain too. A digital edge is a stack of harmonics, and each structure on the board responds to them differently.

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[Dario Fresu @dario_fresu]

Edge stitching vias connected to only one plane can act as stubs that resonate at certain frequencies. Tie each stitching via to each return reference plane (RRP) it passes through.

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[Dario Fresu @dario_fresu]

Cutting the plane under a regulator's switch node cost 6 dB of emissions margin in TI's AN-2155 layout test. GND won't show you why.

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[Dario Fresu @dario_fresu]

Adding copper pours for copper balance? On a dense board with full planes, the balance can already be fine, and thin pour fingers can act like antennas. Check before you pour.

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[Dario Fresu @dario_fresu]

Keep your stackup symmetrical. An unbalanced build can heat unevenly and warp, stressing solder joints. If L2 is a return reference plane (RRP), make L5 one too.

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[Dario Fresu @dario_fresu]

Calculated 50 ohms, then poured copper next to the trace? You changed the line's geometry, so the impedance can shift. Keep pours back or include them in the calculation.

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[Dario Fresu @dario_fresu]

Two signal layers next to each other in the stackup? Put each one on a thin dielectric to its own return reference plane (RRP), and leave a thick dielectric between the two signal layers.

Message me SKOOL and I'll send you the link to our PCB design community.

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[Dario Fresu @dario_fresu]

Power plane far from its return reference plane (RRP)? More spacing raises PDN loop inductance, so impedance climbs at high frequency, where decaps stop helping.

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[Dario Fresu @dario_fresu]

@HSettipall18553 Thanks! If you want to learn more about professional PCB design, join our community here: https://t.co/av3G4V6RdR

[Dario Fresu @dario_fresu]

A connector signal pin needs its return close by, same as a trace over a plane. Put a return pin next to each signal so the fields stay between the wires.

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