In FP8 and FP4, attention is no longer bottlenecked by matrix multiplication. It is bottlenecked by the transcendental and vector math of softmax and the on-chip memory traffic required to shuttle intermediate scores between execution domains:
(Article 🧵) https://t.co/A4ZEmbpCvo
That playbook just hit a physical wall of its own making. By scaling matrix throughput 2× to 4× per generation while leaving Special Function Units (SFUs), vector ALUs, and shared-memory bandwidth behind, chipmakers inverted the attention roofline.
In FP8 and FP4, attention is no longer bottlenecked by matrix multiplication. It is bottlenecked by the transcendental and vector math of softmax and the on-chip memory traffic required to shuttle intermediate scores between execution domains:
When the non-matmul work outruns the matmuls, low-precision attention stops being a GEMM problem.
The industry already voted with production code: drop tokens across the sequence (DSA/QSA via a cheap ReLU indexer with 0 SFU calls), then run the surviving tokens as 100% dense tiles at peak low-bit Tensor Core speed.