Deepak Sharda

I just love silicon |
ASIC& FPGA Engineer

[Deepak Sharda @deeempak]

From 180nm + open-source tools last year to TSMC + scary proprietary tools ahead 🥲🥲 — glad to be part of both.

[Akshar Vastarpara @AksharVastarpar]

I am happy to announce that we (@Vicharak_In) have teamed up with @mnwsth and Prof. Manish Jain from @iitgn to work on TSMC mature nodes and bring some real tape-out projects to reality.

It is only a matter of time before we have successful tape-outs, prototyped. I am delighted that enthusiastic professors like @mnwsth and Prof. Manish Jain exist in India today, with a passion for building technical projects and developing the kind of ecosystem India needs right now.

[Deepak Sharda @deeempak]

@FPGA_Zealot I have tried making a few sin and square wave with it 🙂

[Deepak Sharda @deeempak]

@rrgindeed 😏😏😏

[Deepak Sharda @deeempak]

I have got a 3D printer

[Deepak Sharda @deeempak]

@dhruv_ That's why I bought one

[Deepak Sharda @deeempak]

@RueNahcMohr Yeah I am printing 🙂 it won't be pollution because I won't throw it

[Deepak Sharda @deeempak]

@RueNahcMohr I can't it's like blinking first led with hardware.

But so you want me to not print it.

[Deepak Sharda @deeempak]

Thanks 😊

[ヴァルカン @VulcanIgnis]

shrike-gen now supports flashing thanks to @deeempak of @Vicharak_In

New:

+ Flashing
+ Multi-module support
+ Explicit top module

CLI Makefile scaffolding, build & flashing for Renesas SLG47910V (ForgeFPGA) & the Vicharak Shrike Lite board.

https://t.co/JMLa2mXrfq

#FPGA

[Deepak Sharda @deeempak]

I have been asking renesas for a cli tool for ages to work with Shrike . Seems like it @VulcanIgnis had a better plan he did it himself.

Crazy work , check this out

[ヴァルカン @VulcanIgnis]

Finished shrike-gen for @Vicharak_In Shrike lite board and SLG47910V (Rev BB) FPGAs.

shrike-gen enables Makefile based project creation and build without having to use Renesas' Go Config GUI nightmare.

Finally I am free from the GUI nightmare.

Stay tuned!

[Deepak Sharda @deeempak]

@VulcanIgnis @Vicharak_In @AksharVastarpar Let us know if you need help from us .

[ヴァルカン @VulcanIgnis]

@Vicharak_In
I almost completed writing a full CLI only, makefile based development workflow for shrike. WIP. Some more reversing needed. Once finished I'll post to github.

@AksharVastarpar @deeempak

[Deepak Sharda @deeempak]

@VulcanIgnis @Vicharak_In @AksharVastarpar Hey that is crazy 🫪🫪🫪 less gooooooooo

[Deepak Sharda @deeempak]

@SclMohali 1.2µm ... open source the 180nm
However i hope there will be regular MPW for at least this 1.2µm

[Deepak Sharda @deeempak]

what people don't understand about @Vicharak_In shrike-lite is that even if you don't want to use the fpga you get 37 (23+14) pin on rp2040 which is 11 more then what pico gives , how these +14 pin work is we create a gpio expender in fpga and then they show up as rp's pin extension .

All that for the Same price for pico and that fpga is always there for you to try things on.

Seamless for a user who, does not care about fpga.

[Deepak Sharda @deeempak]

@b1shtream @rcx86 My phone number ends with 57 should I make a 57 bit arch 🥲

[Deepak Sharda @deeempak]

@controlpaths Yup 😂

[Deepak Sharda @deeempak]

@controlpaths At least they powerd this one

[Deepak Sharda @deeempak]

@controlpaths I show a movie and they called an accelerometer 6050 a tracking device and it wasn't even powered 🥲🥲

[Deepak Sharda @deeempak]

@VulcanIgnis @Vicharak_In @AksharVastarpar What would you like to hear

[Deepak Sharda @deeempak]

Wrote this blog on the journey of bringing up the @Vicharak_In Shrike from a bare pcb to full infra it has now.

A lot of problems might sound naive as it was my first board to bring up and @AksharVastarpar decided to believe a newbie to do the job.

https://t.co/IhJ52M6Bj3