ICICLE-Snark: The Fastest Groth16 Prover in the World ⛷️
We pushed Groth16 acceleration to the extreme—ICICLE-Snark sets a new standard for proof generation speed.
Link to repo: https://t.co/AERBI7ycOz
❄️ Benchmarks, manual, and more inside:
https://t.co/54HXxKcvAW
256-bit fields 🤝 AVX-512 = 🚀
The Jolt team built an AVX-512 library for 256-bit modular arithmetic with up to 16x acceleration and we're open sourcing to accelerate the ecosystem!
Background
It's common in SNARKs to do operations over very large vectors of field elements. The core of the Jolt workload does element-wise vector arithmetic over vectors with a magnitude equal to the number of RISC-V instructions in the program trace.
AVX-512 is an instruction set extension with expanded registers: 64 bits -> 512 bits. The idea is that more computation can be done per clock cycle of the CPU. These special registers are known as SIMD registers or Single Instruction Multiple Data.
The STARK community has long focused on packing multiple 32-bit field elements into SIMD registers to increase compute efficiency per CPU cycle. Plonky3 and Binius take advantage of these registers via their PackedField backends. New fields like the Circle STARK M31 field have been created to leverage these instructions even more effectively.
Big Fields
Jolt famously uses "big fields". Meaning we require 256 bits to represent each field element or four 64-bit x86 registers. These are computationally less efficient than the 32-bit fields. 256-bit fields require ~80 clock cycles per multiplication where 32-bit fields require 2-10 cycles.
Jolt is not the only user of 256-bit fields in prod. The Groth16 provers (typically the final recursive layer of STARK-based zkVMs) depend on the Bn254 256-bit field thanks to the Ethereum friendliness.
Vectorized Fields
A few months ago @moodlezoup and I figured it was plausible to fit two 256-bit field elements into a 512-bit register and perform montgomery arithmetic on two at once. We were hoping that we'd see just under a 2x speedup.
@huitseeker from the @argumentxyz team pointed us to the perfect man for the job: Dag Arne Osvik.
Dag Arne helped us prove out this concept and it far exceeded our initial expectations. Initial results below.
Unfortunately the speedup decays when we split the vector operations over many cores. We believe this is due to saturation of the memory bus: when splitting the workload across 32 or 64 cores, the operation is no longer compute constrained, but rather memory constrained. As a result, when using 64 cores the AVX-512 accelerated version drops to a 1.1x speedup for element-wise operations, and 2-3x for aggregation operations.
In practice we see around a 2x speedup for sumcheck at max parallelism on a 64 core machine. Details available at https://t.co/TJhFY6FPlK. We have not yet integrated this into Jolt but it's coming.
Ecosystem Wide
The exciting news is that this work should be reusable for Groth16 prover backends such as Gnark and RapidSnark.
@zkgbo is working on this for Gnark https://t.co/KwUIpCBsR3 and we're looking for someone to help with Rapidsnark. If you can help or have a different 256-bit workload that you'd like to support, please reach out!
The library is available at https://t.co/9rNfn1qTI1. Currently it only supports Rust over the Bn254 scalar field, but it's easy to add new FFI bindings or other 256-bit moduli. Let us know what you need!
🎉Congratulations on the mainnet launch of @taikoxyz , the first based rollup protocol deployed on the #Ethereum.
🥳Our featured 'BCR explorer' has also synchronized with the mainnet launch.
Wait for what? Rock it up!!🤟🥁
https://t.co/BFiOKjRUAM
SuperScalar won a @z_prize special award for the best performance in MSM over the BLS12-377 curve using FPGA, showcasing the SuperScalar team's leading technology in accelerating zero-knowledge proofs.
Thanks to the organizational efforts of @z_prize and @cysic_xyz.
🎉Great, excited! I am honored to have participated in the zprize competition, and together we won a @z_prize special award for the best performance in MSM over the BLS12-377 curve using FPGA. @SuperScalar_io
🩷This is a memorable experience!Thanks to @z_prize and @cysic_xyz.
SuperScalar won a @z_prize special award for the best performance in MSM over the BLS12-377 curve using FPGA, showcasing the SuperScalar team's leading technology in accelerating zero-knowledge proofs.
Thanks to the organizational efforts of @z_prize and @cysic_xyz.