@dougallj@FritzchensFritz might be able to make some inferences about what all the SRAMs are for, or about smaller structures that arent SRAMs [i can spot at least a couple of them at 5x]
(whether or not that's useful or interesting and worth the time is another question!)
@FelixCLC_ maybe don't put the phrase "backdoor-free" on your landing page if your very detailed technical documentation is not also on the landing page
@lauriewired@FelixCLC_@G_melo_ding hopefully there are not subtle bugs in whatever firmware handles your voltage scaling, otherwise... surprise, now all your clocks are acting funny, which seems like another tricky thing to think about :(
@lauriewired@FelixCLC_@G_melo_ding seems especially tricky when you rely heavily on DVFS, and when you also intend to let users overvolt/overclock parts! https://t.co/JN9sfMTQmy
I have just made our latest product (Modos Flow) open-source: https://t.co/FYoKwDrdlN. With complete source code (for both MCU and FPGA) and PCB design source file in KiCAD. It's a 300-ppi Eink portable monitor with 60Hz refresh rate and touch screen:
@mu_chrinovic@ivanrouzanov@ArturS03812590 if you have younger instructions that are complete *before* you recognize an older instruction will fault, you need some way to recover the state of the register map used by the faulting instruction