Charles Eric LaForest, PhD

FPGA Design Engineer. Working to improve the state of digital logic design: INACTIVE. PLEASE EMAIL: [email protected] )

[Charles Eric LaForest, PhD @elaforest]

I'm writing an online book: "FPGA Design Elements",
which provides a reference library of fundamental digital logic design elements. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation.
https://t.co/YQg8JiIZ4P
https://t.co/xGJ7o4KZGf
#FPGA

[Charles Eric LaForest, PhD @elaforest]

I'm not monitoring this account for now.
Please email me at: [email protected]
Or find me at https://t.co/A1kipRr7X8

[Charles Eric LaForest, PhD @elaforest]

@cmmonco Can't help you there, sorry.

[Charles Eric LaForest, PhD @elaforest]

@cmmonco Not yet. :) Email me if you are interested.

[Charles Eric LaForest, PhD @elaforest]

Here's a common workhorse for designs: a Pipeline FIFO Buffer. Any FIFO depth is allowed, not only powers-of-2. The input-to-output latency is 2 cycles. Can function as a Circular Buffer. The tricky bit is the read output, which is registered for speed.
https://t.co/knzHAzuXkD

[Charles Eric LaForest, PhD @elaforest]

A Pipeline Half-Buffer: A single pipeline register with ready/valid handshakes. Decouples the input and output handshakes (no combinational path), but does not allow concurrent read/write like a full Pipeline Skid Buffer.

https://t.co/i1W66wMeUB

[Charles Eric LaForest, PhD @elaforest]

Here's the most important pipeline building block: a Skid Buffer. It decouples two sides of a ready/valid handshake to allow back-to-back transfers without a combinational path between input and output, thus fully pipelining the path.

https://t.co/CE7DurAjqy

[Charles Eric LaForest, PhD @elaforest]

@ptrschmdtnlsn @MaskedTorah @taktoa1 I haven't had to build hardware sorting networks before, but this is part of a bitonic sort, of course. The only advice I can give is not to aim for algorithmic optimality as I expect your k to be small, but for least logical effort. Simpler, faster hardware tends to win.

[Charles Eric LaForest, PhD @elaforest]

@TudorTimi I wonder how much of that comes from legacy Verilog-1995 codebases, which is really too limited a language for modern hardware design. (I hold to a subset of the synthesizable subset of Verilog-2001. Modularization takes care of the rest.)

[Charles Eric LaForest, PhD @elaforest]

I'm writing an online book: "FPGA Design Elements",
which provides a reference library of fundamental digital logic design elements. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation.
https://t.co/YQg8JiIZ4P
https://t.co/xGJ7o4KZGf
#FPGA

[Charles Eric LaForest, PhD @elaforest]

@ptrschmdtnlsn And you also have observed that it's never worth "saving a cycle" when the Fmax impact affects all unrelated operations. "single-cycle" as optimality is a red herring.

[Charles Eric LaForest, PhD @elaforest]

@ptrschmdtnlsn That's the general idiom, yes. Compute the next state from the current state and current inputs. Short-circuit as needed, but carefully. But the real solution here is to extract the arbiter from the FSM into it's own module. https://t.co/vyNSpTHvN4

[Charles Eric LaForest, PhD @elaforest]

@ptrschmdtnlsn I do just that with hardware counters. 64 bits at 100 MHz takes 5500 years to rollover, and I don't think the system uptime will exceed that. :) Makes calculating time intervals trivial.

[Peter Schmidt-Nielsen @ptrschmdtnlsn]

Clock stability is essential: with a 1 GHz clock you get 1ns on your critical path to close timing. But if your clock's 99.9999999999th percentile shortest period is even just 10% shorter then you *must* get everything done in 900ps, or your circuit will fail within an hour.

[Charles Eric LaForest, PhD @elaforest]

Here is a module which extends the 1-to-N Differential Deserializer by packing two consecutive differential N-bit deserialized words into one differential 2N-bit word and extending the bitslip word-alignment logic to support this double-width word. https://t.co/QdRyQVKneF

[Charles Eric LaForest, PhD @elaforest]

@ptrschmdtnlsn I'd avoid Spartan and stick to Series 7 (Artix/Kintex/Virtex). Pick a footprint that gives you options to go to a smaller or larger part if needed.

[Charles Eric LaForest, PhD @elaforest]

When aligning multiple data channels, you need to pass them through variable-delay shift registers. This is where using an FPGA's built-in shift-register hardware is a must, since using LUTs+FFs ends up being the large majority of the deserializer area!
https://t.co/x9WIu1w52W

[Charles Eric LaForest, PhD @elaforest]

A pipeline serial to parallel converter. Reads in multiple serial words and signals when the last input word has been read-in and a new, wider output word is ready to be read-out, in the same cycle if necessary to receive an uninterrupted serial stream.
https://t.co/SiYoxOUbI1

[Charles Eric LaForest, PhD @elaforest]

A deserializer for differential data, with a configurable 1:N ratio, SDR or DDR data rate, and independent positive and negative data polarity input delays and deserializers, which enable bit and word alignment training later on.
https://t.co/BVhZRiRbJh

[Charles Eric LaForest, PhD @elaforest]

An IDELAYCTRL instance for calibrating IDELAY2 blocks. This is the first step to high-speed interfaces on Series 7 AMD/Xilinx FPGAs.
https://t.co/ByAjf8ZEfV

[Charles Eric LaForest, PhD @elaforest]

https://t.co/A1kipRr7X8 now supports HTTPS! It's still a static site without cookies or Javascript or any inputs, but I was getting reports of problems with browsers, corporate networks, and Google not liking the absence of SSL. Enjoy more easily now!