johnfpga

[HackerNoon | Learn Any Technology @hackernoon]

"Top 4 HDL Simulators for Beginners" by @fpgatutorial https://t.co/xbDSKPqRmt #fpga #asic

[johnfpga @fpgatutorial]

Take a look at our latest SystemVerilog tutorial where we talk about parameterized modules and generate statements #fpga #systemverilog
https://t.co/SeDjitzREf

[OneSpin: A Siemens Business @OneSpinSolution]

Lieben Sie RISC-V?

In this piece for #German publication @aeaktuell, @NicolaeTusinsc1 explores the #verification of #RISC_V cores, #security, #functionalcorrectness, #opensource challenges

https://t.co/0utWi29xXN

@risc_v semiEDA #formalverification #sicherheit #funktionalität

[johnfpga @fpgatutorial]

In this week's tutorial, we take a look at SystemVerilog tasks #fpga #systemverilog

https://t.co/AIIOoh2rDn

[johnfpga @fpgatutorial]

In our latest SystemVerilog tutorial we look at functions and how we can use them to write reusable code.
#fpga #systemverilog

https://t.co/SacbDZYmRZ

[johnfpga @fpgatutorial]

This week we take a look at the different types of loop which we can use in SystemVerilog #fpga #systemverilog

https://t.co/yVxwaf6Zjv

[Altera @AlteraFPGA_]

Intel® Agilex™ FPGAs with high-performance Crypto Blocks target Infrastructure Processing Units (IPUs), SmartNICs, and 5G Networks

https://t.co/1YU8gSM6MX

[johnfpga @fpgatutorial]

In our latest post on SystemVerilog for FPGA design we look at the if statement and case statements #fpga #systemverilog
https://t.co/HJHNaAdT0S

[HighLevelSynthesis @HighLevelSynth1]

Digital System Design with #Xilinx #VitisHLS for #FPGA

https://t.co/MC4C3SzBi0

@DigilentInc @Avnet @XilinxEMEA @XilinxInc @IntelFPGA @hipeac @2021Fpl @silexica @SilexicaJapan @cathalmccabe @FPGA_BOT
@fpgatutorial @ATaylorCEngFIET @splinedrive @CindyZou10

[johnfpga @fpgatutorial]

Check out our latest tutorial post where we talk about the different types of always block which can be used in SystemVerilog #fpga #systemverilog
https://t.co/G6L1BPX09F

[Cathal McCabe @cathalmccabe]

Introducing the #XACC_TechTalk summer series on #Xilinx Adaptive Compute.
First two sessions will cover FPGA OS Abstractions, Data centric programming and #Vitis UDP, TCP/IP and distributed ML from #ETHZ and Xilinx speakers.
Register free: https://t.co/986VlB6foo

[RISC-V International @risc_v]

We love a #RISCV tutorial! Learn how to install a #RISCV #processor on your FPGA board: https://t.co/ge514ZkiRV

[YosysHQ @YosysHQ]

Heya o/ Check out our latest blog post on our new Appnote! Also, we now have a blog (https://t.co/NNM7dPQMjV) and write appnotes (https://t.co/yA7d5Yd08p). https://t.co/LuUwRVFCPa

[johnfpga @fpgatutorial]

Nice introductory article on using Xilinx multi-gigabit transceivers

https://t.co/IVK3zgSNTo

[Unai @unaimarcor]

To all the VHDL people out there, do you now about https://t.co/ROBbjbFOiP? That's the site of the VHDL Analysis and Standardisation Group (VASG). We are gathering and organising Bug Reports and Capability/Feature Request for the next revision of the language (202X). Come by!

[Juan Gonzalez @Obijuan_cube]

VideoBlog. Capítulo 54: FPGAs y Constantes. Colección iceK (3/4). Ejemplos hola mundo en diferentes placas https://t.co/abYmeUyZfy

[RISC-V International @risc_v]

Learn about how to build a #RISCV CPU from scratch. @ten_filip of @IEEESpectrum walks you through how to do this here: https://t.co/1ybtcUjWgM

[YosysHQ @YosysHQ]

🧑‍💻Our next interview guest will be @wavedrom! https://t.co/iBRRbeUdKT

[johnfpga @fpgatutorial]

In this week's post we look at continuous assignment and how we can use it to model combinational logic in SystemVerilog #fpga #systemverilog

https://t.co/dEaSVQkGMg

[STH @ServeTheHome]

The Xilinx Kria KV260 FPGA-based Video AI Development Kit is a huge step in bringing FPGA solutions to a wider developer community https://t.co/DUvWtS0jLB @XilinxInc #FPGA #AI