TSMC Teams Up with Ibiden and Innolux to Push CoPoS — Reportedly Flooring the Accelerator in Glass Substrates
To meet robust AI chip demand, TSMC is not only ramping CoWoS advanced packaging capacity but has, for the first time, disclosed progress on its "glass substrate" technology. The company further signaled that the next-generation advanced packaging battle is gradually shifting from CoWoS to CoPoS (Chip-on-Panel-on-Substrate), as it moves to build out a complete ecosystem ahead of the curve.
According to equipment-side sources, TSMC recently shared a "Glass Substrate Development for CoWoS" program with its supply chain. It has confirmed a partnership with ABF substrate giant Ibiden and panel maker Innolux to jointly validate the feasibility of introducing glass substrates into next-generation CoWoS advanced packaging. The aim is to address the warpage, thermal management, signal transmission, and power delivery challenges that loom over future large-die AI chip packaging.
At the same time, the move reflects rapidly intensifying customer demands around technical specifications and capacity, as well as mounting competitive pressure from Intel and Samsung Electronics. That pressure has finally pushed TSMC—long known for advancing R&D on a "cautious, not aggressive" basis—to step on the accelerator.
Glass substrates are viewed as a key technology for the "post-CoWoS era" thanks to their low warpage, low thermal expansion, high rigidity, and excellent signal and power-delivery characteristics. Supply chain sources say the three-way collaboration among TSMC, Ibiden, and Innolux, together with simulation validation, has shown that glass substrates can improve the package-warpage indicator COP (Chip on Package) by 16%, lower the effective coefficient of thermal expansion (Effective CTE) by 19%, and raise the effective modulus (Effective Modulus) by 31%.
On power integrity, resistance fell by 27% and inductance by 42%. Overall, introducing glass substrates can deliver a marked improvement in package performance (PKG Improvement).
TSMC nonetheless stressed that continued research and validation are still needed on glass thickness (Glass Thickness) and large-size CoWoS layout (Large-size CoWoS Layout). While full-scale mass production remains some distance away, this marks the first time TSMC has publicly disclosed joint glass-substrate validation results with Ibiden and Innolux—signaling that glass substrates have formally entered the industrialization-validation phase.
Industry observers added that the 16% COP improvement indicates package warpage is being effectively controlled. As AI GPU dies grow ever larger—with NVIDIA's GB200, GB300, and the now-ramping Rubin platform all expanding in package size—the importance of package flatness and warpage control has risen sharply. The performance glass substrates show in reducing warpage should help lift the yield and reliability of large packages.
In addition, the 19% reduction in SBT effective CTE shows improved matching between the glass material and the silicon die.
Today, silicon's CTE differs substantially from that of conventional organic substrates, making it prone to stress under temperature swings that can compromise package reliability. By contrast, glass has a CTE closer to that of silicon, which helps reduce thermal stress and mitigate cracking and solder-joint fatigue. The 31% gain in effective modulus means higher overall rigidity, providing better structural support. In particular, as HBM stack heights keep increasing, substrate rigidity is becoming a critical condition for supporting large packages.
The test sample TSMC used this time featured a 0.8mm glass core substrate, a package spec of 5x reticle CoW, and an overall package size of 85×110mm—an AI GPU package-class footprint. TSMC specifically emphasized "No SeWaRe (severe warpage) & Delamination," meaning no severe warpage or delamination/peeling—both yield killers—occurred during testing.
For glass substrates, material bonding reliability has always been a key challenge, so maintaining a stable structure at large package sizes demonstrates considerable progress in technical maturity.
Another focus of the program was the comparison between Glass-SBT and Organic-SBT. TSMC noted that Glass-SBT achieves "thin but better COP," whereas Organic-SBT shows "thick but worse COP"—glass substrates can stay thinner while simultaneously improving package flatness and reliability.
The partner roster also hints at the direction of the future supply chain.
Ibiden currently sits in the critical substrate supply chain for NVIDIA and AMD AI chips and is regarded as a key player in industrializing glass substrates. It previously announced a ¥500 billion investment to expand its new Ono plant in Gifu Prefecture, dedicated to high-end packaging substrates for AI servers—underscoring its strong ambitions in the AI advanced-packaging market. Innolux's inclusion on the partner list is likewise seen as an important step toward staking out the next-generation glass-substrate battlefield.
Industry sources say the biggest challenge for glass substrates is not the glass itself but Through Glass Via (TGV) technology. Because glass is fundamentally an insulator, tens of thousands of TGVs must be formed to create vertical conductive paths before signal and power transmission becomes possible.
Glass is also both hard and brittle, making it prone to micro-cracks during processing that can affect reliability and yield. As a result, via forming, copper-fill quality, and long-term thermal reliability are considered the three core hurdles to mass-producing glass substrates.
Separately, Intel began investing in glass-substrate R&D more than a decade ago and is regarded as the earliest and deepest player globally. Its glass-substrate pilot line in Arizona is gradually moving toward commercialization, and Intel is aiming to win AI GPU and ASIC customer orders through glass substrates and ultra-large chiplet packaging.
Samsung Electro-Mechanics (Semco) established a glass-substrate pilot line in 2025 and has set up a joint venture with Japan's Sumitomo Chemical group to build out a glass-substrate supply chain ahead of the market.
$TSM
But Bubble Boi says it is impossible, so it must be that $TSMC engineers got scammed by PLP suppliers
Maybe people need to understand that wafers will still be round. What changes is the PACKAGING
You make dies on a round wafer, which is then diced into individual chips. After that, you package those chips on panels
Before, you would use a round 300mm silicon wafer to make interposers. But when you place large square or rectangular interposers on a round wafer, you waste a lot of area near the edges
If you package on a rectangular panel, you process more packages per batch, creating less edge waste, better area usage, and a lower cost per package
Nobody ever talked about rectangular wafers. This is about panel-level PACKAGING
Checked overnight market. Damn lol.
Guess I need to stay up another hr to push leverage in premarket.
Prob size up WOLF and AAOI. Re-enter Enphase. Maybe re-enter NVTS.
Concerned dumb ppl falling for Navitas CEO TAM bullshit. Their SiC is garbage. Only GaN portfolio of value.
Morgan Stanley: “Optical Content Growing. Regardless of Architecture.”
Morgan Stanley’s latest optical report pushes back on the idea that the CPO vs. NPO debate changes the broader demand trajectory for optical content. The core argument is that investors may be over-indexing on architecture timing, while the more important variable remains bandwidth growth. Whether the market ultimately scales through pluggable optics, NPO, CPO, OBO, or hybrid architectures, the need for higher bandwidth should continue to drive more optical engines, lasers, and related content per GPU/rack.
The report acknowledges that CPO adoption has meaningful timing and execution uncertainty. Packaging complexity, lower yields, troubleshooting difficulty, ecosystem immaturity, and customer reluctance around serviceability all remain real constraints. That is why Morgan Stanley frames the current debate less as a question of whether optics wins and more as a question of when and through which architecture the industry scales.
Importantly, the report still points to optical content rising materially as AI networks move from current architectures toward copper/CPO hybrid and eventually fuller CPO configurations. Morgan Stanley estimates optical engines per GPU increase substantially across each step of that architecture transition, with the demand driver tied less to a specific design choice and more to the underlying bandwidth requirement.
The market reaction in optical names appears to reflect concern that slower CPO timing could delay the upside case. Morgan Stanley’s framing is more balanced: conservative assumptions on CPO timing may keep stocks away from the most aggressive bull cases for now, but the underlying content expansion remains intact. For $LITE, $COHR and $GLW, the debate is not whether AI infrastructure requires more optics, but how quickly that demand converts into revenue as architectures evolve.
Abstract of “Passives: AI to Boost High and Low”
* Driven by AI and the recovery of automotive/industrial.
we expect the cycle to be potentially stronger than the peak levels seen in 2018 and 2023.
* AI will lengthen the lead-time and lower the yields, leading to >3x capacity consumption (i.e., low/high-cap MLCCs ~6/~25 days with yields of 99.5%/95-98%, vs. AI’s MLCC >50 days with yields of ~50%).
Key data
l # of capacitors to increase from ~300k in GB200 NVL72 to ~550k in VR200 NVL72
l AMD and/or ASIC’s content will increase by ~50% for the next generation
l # of resistors to increase significantly to ~50k in VR200 NVL72.
l Spot price: We’ve seen 104 price increase by >3x in past 3 weeks, 106 rose by >2x. As a comparison, the spot-market for certain products surged by as much as 20x at peak levels in 2018.
l Price raise for ODMs started for consumers and servers: We expect low-cap prices (i.e., 102-104) for ODMs to be up by 5-100% in 3Q26, followed by 15-30% for higher-cap 105/106 Industrials/servers in 4Q26.
l Resistors to kick off price hikes in 3Q26, likely ~50% for ODMs
#MLCC #MURATA #Taiyo #Yageo
Simple, the Trump admin cannot roll out new restrictions/export controls targeting China because the Chinese can/will retaliate
We are not in the H100 era, where the supply chain was largely concentrated in Taiwan/Korea/Japan
Becuz of shortages, Nvidia & hyperscalers have been forced to qualify Chinese suppliers, especially in the PCB supply chain and electrical components like transformers
China had a chokehold on optics (optical fibers and transceivers) from the beginning, and this is just getting amplified as optical content in DCs is increasing
Coherent CEO went to China with the Trump delegation, asking for InP for lasers
I want u guys to study the optical fiber preform supply chain, and who are the largest suppliers
Btw, Chinese exposure is also spreading to other parts of the AI supply chain
High end MLCCs use Dysprosium Oxide and China supplies most of it to Japanese producers
Tungsten ban from China is causing the prices of WF6 gases to shoot up
If PTFE is finalized for M9/M10 CCL, then Shengyi and Chinese PTFE suppliers will have a huge chokehold over Nvidia
Google is in talks with Envicool for the supply of cooling components
If diamond-copper composites are adopted as heat spreaders for GPUs, then China will establish a chokehold there as well, since most of the synthetic diamonds are produced there and China is at the cutting edge of this tech
I haven't even talked about the use cases of gallium, germanium, tellurium, antimony, bismuth, fluorine, terbium, yttrium, ferrite cores in the AI supply chain, and how China has a chokehold there
The Trump admin is constrained in a lot of ways and can't unilaterally export control stuff
People interested in coherent lite as a scale up solution should follow this startup, they’ve done some interesting R&D out of UCSB
https://t.co/hkhUwmDQ0R
Optical interconnect is moving closer to the compute engine.
From FRO and TRO to LPO, LPO with CPC, and ultimately CPO, the direction is clear: reduce electrical signal distance, remove unnecessary DSP overhead, and improve power efficiency.
At 1.6T, power can potentially drop from 25W in full-retimed optics to around 7W with co-packaged optics.
For AI data centers, optics is no longer just a connectivity layer. It is becoming a core part of compute infrastructure.
#AI #DataCenter #OpticalInterconnect #CPO #LPO #Semiconductors
"Chinese open source models are about to fall badly behind as Mythos level models employ anti-distillation."
This will age very poorly
Distillation has stopped being a capability driver for GLM, Deepseek, Moonshot
U can try v4, K2.7 & GLM 5.2 to test this
If a new/exotic technology is competing with capital, capital almost always wins.
New/exotic tech needs to be SIGNIFICANTLY better than the existing solution.
In the context of components within communication systems, that typically means noise performance.
Based on the evidence I see in the past week, the optical story has gotten better, not worse.
Scale-out CPO seem to be on track and pushing Lumentum’s revenue this quarter to the high end of their guidance.
Scale up CPO was never delayed, as it was always shipping with Feynman, not Rubin Ultra, in the first place.
And NPO does not cannibalize CPO. Instead, it cannibalizes the Kyber racks, making it purely incremental content for optics.
TSMC's #CoPoS is moving fast, and the opportunities for Taiwan suppliers are taking shape. CoPoS replaces traditional round glass carrier with a square panel format, pushing utilization rates above 75%.
More on glass material development: https://t.co/Na9XtpNK8Q 🔗
🍪 TWiC: Controversial Packaged Optics (free)
A look into why Spectrum-X CPO is cruel and unusual engineering punishment.
And what that means for the future of CPO.
https://t.co/teNwh7wPXL