wrote a pair of PLSE blog posts explaining the basics of Verilog syntax (post 1) and semantics (post 2) for a PL audience:
syntax: https://t.co/2HmS3N0vtw
semantics: https://t.co/z95xBOJihX
feedback welcome! from a PL perspective, Verilog is fascinating.
i defended! if you'd like to learn more about the automatic generation of compiler backends from models of hardware, check it out:
https://t.co/r4RJgARVVP
@schowdhary02 in the past was Glenside, which models deep learning accelerator computations as program rewrites, and using those rewrites to find places to invoke the accelerator:
orig paper: https://t.co/Dn8FugbVPs
used in a larger project: https://t.co/lCL7sUDj9u
app readers: lookout for my longtime mentees Andrew Cheung (https://t.co/vxE0VYCQpk) and Vishal Canumalla (https://t.co/SIVPHzvAzF) who have experience w/
- paper writing, eval building
- ML *and* hardware compilers
- prog. synth.
- eqsat
(bonus: they're just plain good people!)
@PLDI@ISCAConfOrg @ben_kushigian @vcanumalla@ztatlock by the way -- both Andrew (https://t.co/vxE0VYCQpk) and Vishal (https://t.co/SIVPHzvAzF) are applying for PhDs this year. it's been a joy to work with them both over the past few years, and they will both make stellar PhD students. be on the lookout for their applications!
Generate Compilers from Hardware Models!
https://t.co/8M64crRlJU
the video of my talk at the 2023 PL for Architecture workshop (@PLDI /@ISCAConfOrg ) is up! thanks to my coauthors @ben_kushigian, @vcanumalla, Andrew Cheung, Renรฉ Just, and @ztatlock & the PLARCH organizers!
@notypes and I are starting a brand new stream: TheForkJoin! First stream will be THIS SATURDAY (July 15th) at 10am PT.
๐๏ธ: https://t.co/X4vwCbV21e
tv: https://t.co/LUZiwkIo0D
This time we'll chat with @shwestrick about making parallel functional programming wicked fast. (1/2)