#Zen6c - Twitter Hashtag

6 days ago

#AMD released the "AMD EPYC SERVER CPU ARCHITECTURE AND PERFORMANCE OVERVIEW" White Paper: https://t.co/KV81rVjqV6 #Zen6 #Zen6c #AVX512 #x86EAG #EAG #ACE

InstLatX64's tweet photo. #AMD released the "AMD EPYC SERVER CPU ARCHITECTURE AND PERFORMANCE OVERVIEW" White Paper:
https://t.co/KV81rVjqV6
#Zen6 #Zen6c #AVX512 #x86EAG #EAG #ACE https://t.co/qcK8ksHAf6

InstLatX64 @InstLatX64

11 months ago

I think #APX has bright future ahead of it. Not a clear commitment, but a very good sign: it appeared in Mark Papermaster's presentation along with "ACE" which seems to be a relabeled #AMX #OCP2025 #AMD #x86EAG #Zen7 https://t.co/X2roicnCvm https://t.co/58VpCSkeYS thx, @ravigiri!

InstLatX64's tweet photo. I think #APX has bright future ahead of it.
Not a clear commitment, but a very good sign: it appeared in Mark Papermaster's presentation along with "ACE" which seems to be a relabeled #AMX
#OCP2025 #AMD #x86EAG #Zen7
https://t.co/X2roicnCvm
https://t.co/58VpCSkeYS
thx, @ravigiri! https://t.co/8BCqXyQPaw

1

68

6

20

12K

0

84

12

28

5K

InstLatX64 @InstLatX64

15 days ago

#AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 51h, Revision B0 Processors" v0.45 58264 pdf (#Zen6c CPUID B50F10) for socket #SP7 #Venice #EPYC 9006 w/ 32-core + 128MB L3 #Monarch CCDs: https://t.co/oNM7ocEtE7

InstLatX64's tweet photo. #AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 51h, Revision B0 Processors" v0.45 58264 pdf (#Zen6c CPUID B50F10) for socket #SP7 #Venice #EPYC 9006 w/ 32-core + 128MB L3 #Monarch CCDs:
https://t.co/oNM7ocEtE7 https://t.co/sbYtUkRHiI

InstLatX64 @InstLatX64

7 months ago

#AMD refreshed the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 02h, Revision C1 Processors" to v0.49 57238 pdf (classic #Zen5, CPUID B00F2x) with socket #SP6, #TR5 data: https://t.co/ZVxdUTLRuV 84-core #EPYC8005 #Sorano is based on 7-core enabled #Eldora CCDs

InstLatX64's tweet photo. #AMD refreshed the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 02h, Revision C1 Processors" to v0.49 57238 pdf (classic #Zen5, CPUID B00F2x) with socket #SP6, #TR5 data:
https://t.co/ZVxdUTLRuV
84-core #EPYC8005 #Sorano is based on 7-core enabled #Eldora CCDs https://t.co/DyliXvIyFV

1

16

1

4

5K

1

21

3

0

5K

InstLatX64 @InstLatX64

about 2 months ago

https://t.co/O1s37LRpjG confirmed these old rumors: - #Medusa1 is FP10/AM5 - #Medusa2 is FP10 - #OlympicRidge is AM5 #Zen6 #Zen6c https://t.co/BSOlXQvXFZ

InstLatX64's tweet photo. https://t.co/O1s37LRpjG confirmed these old rumors:
- #Medusa1 is FP10/AM5
- #Medusa2 is FP10
- #OlympicRidge is AM5
#Zen6 #Zen6c
https://t.co/BSOlXQvXFZ https://t.co/Hpg6x8uSid

InstLatX64 @InstLatX64

3 months ago

#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 https://t.co/ThbENc8lK6

2

28

2

5

13K

3

50

11

10

8K

InstLatX64 @InstLatX64

about 2 months ago

I converted the #AMD #Zen6c #Monarch CCD configurations to a more conventional 4x8 layout. I still find it hard to believe that a 32-core chip made with a brand new process doesn't have redundant cores.

InstLatX64 @InstLatX64

3 months ago

It's hard to let go of this 3x11 #Zen6c #Monarch CCD configuration idea, because it simply explains the unusual number of cores in CCDs by disabling rows and columns. It's not great for L3 latency, but I think something similar is needed for the risk of the new TSMC N2 process.

InstLatX64's tweet photo. It's hard to let go of this 3x11 #Zen6c #Monarch CCD configuration idea, because it simply explains the unusual number of cores in CCDs by disabling rows and columns. It's not great for L3 latency, but I think something similar is needed for the risk of the new TSMC N2 process. https://t.co/zw6zbvi4Xa

4

21

5

8

6K

4

26

4

2K

InstLatX64 @InstLatX64

3 months ago

It's hard to let go of this 3x11 #Zen6c #Monarch CCD configuration idea, because it simply explains the unusual number of cores in CCDs by disabling rows and columns. It's not great for L3 latency, but I think something similar is needed for the risk of the new TSMC N2 process.

InstLatX64 @InstLatX64

3 months ago

My attempt to assign CCD types on 6th Gen #AMD #EPYC SKUs based on core count, L3 size, and frequency: 9 #Monarch, 4 #Powderhorn configuration #Zen6 #Zen6c #Morpheus

InstLatX64's tweet photo. My attempt to assign CCD types on 6th Gen #AMD #EPYC SKUs based on core count, L3 size, and frequency:
9 #Monarch, 4 #Powderhorn configuration
#Zen6 #Zen6c #Morpheus https://t.co/zvuMZl65n9

1

25

2

6

6K

4

21

5

8

6K

InstLatX64 @InstLatX64

3 months ago

My attempt to assign CCD types on 6th Gen #AMD #EPYC SKUs based on core count, L3 size, and frequency: 9 #Monarch, 4 #Powderhorn configuration #Zen6 #Zen6c #Morpheus

InstLatX64 @InstLatX64

8 months ago

This snow report was the inspiration for this #AMD #Zen codename table. Sources included. #Zen2 #Zen3 #Zen4 #Zen5 #Zen6 #Zen7

1

26

2

10

6K

1

25

2

6

6K

InstLatX64 @InstLatX64

3 months ago

Until the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type. But supposing 11x3 core within the #Monarch CCD makes this a yield optimization. https://t.co/Gfi9K61uFy

InstLatX64's tweet photo. Until the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type.
But supposing 11x3 core within the #Monarch CCD makes this a yield optimization.
https://t.co/Gfi9K61uFy https://t.co/fpCcB3iyna

HXL @9550pro

3 months ago

EPYC 9006X

1

65

6

7

10K

1

29

2

7

4K

Top Tweets for #Zen6c

Last Seen Hashtags on Sotwe

Trends for you

Most Popular Users