Top Tweets for #ZeroToASIC
#Tandon researcher @kiwihammond & #Phd candidate Jason Blocklove discuss how conversations with #AImodels can help create #microprocessingchips with @matthewvenn on #ZerotoASIC
#NYUTandonMade
https://t.co/BuWthAxZhx
FP_ALU GDS-II design using the Caravel User Project based on @GoogleOSS OpenLane to automate flow with SkyWater130 and GF180MCU PDK #zerotoasic
Google is sponsoring a series of no-cost Open MPW shuttle runs for the GF180MCU PDK.
The first shuttle will be a test with submissions open from October 31st to the beginning of December.
Check out the blog for more details β https://t.co/prrEgViKvN
FPGAs have this and S4GAs have this. Alas the implementation of S4GAs for #ZeroToASIC and #TinyTapeout in 0.1mm2 / 0.01mm2 130nm ASIC can't store many LUT configuration frames on die.
@tnt @matthewvenn Thank you for the suggestion. Just not a lot of area for any config bits in the #TinyTapeout version of S4GA.
In earlier #ZeroToASIC MPW version I use constantly recirculating shift registers of the low fanout D-FF cell to avoid read/write/CE access circuits. 1/
7 segment decoder ASIC design using the Caravel User Project that works off openlane to automate RTL to GDSII flow with SkyWater PDK which designs in 130nm scale. Generated this view with GDS3D #zerotoasic
Thank you @matthewvenn for this awesome piece of MPW-1. I will treasure and use it. Real meetings and conferences enable the exchange of such goodies again. Awesome FSiC in Paris! #FSiC2022 #sky130 #zerotoasic
When I said I managed this thanks to a lot of help from the community, I was primarily talking about @matthewvenn's #ZeroToAsic course.
There is just no way I would have even attempted it without that.
https://t.co/wpNOcy2VNY
MPW5 submission closed. Now: Wait for Spring, Summer, Autumn to be gone. Where is the fast forward button to next christmas? @matthewvenn @Efabless #MPW5 #ZeroToASIC
Finally got going on @matthewvenn βs #ZeroToASIC course and Iβm impressed so far, both with the material and the engagement of the community of likeminded folks in that space
My first experimental ASIC silicon design is going to tape out soon. Looking forward for my own chip :)
All thanks to @matthewvenn and his remarkable #ZeroToASIC course and help with this project!
Repo: https://t.co/fcU4oha1zm
#efabless #mpw3 #OpenSourceHardware #OpenLane
Yay! Just enrolled to @matthewvenn Zero to ASIC course! So much to learn and a brand new world of open hardware.
Canβt wait for it.
#ZeroToASIC #OpenSource
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