#basic52 - Twitter Hashtag

over 1 year ago

We can't use both UART and I2C simultaneously in #CH552E since SDA P1.6 shares with UART. Reassigned SDA pin to P1.4 and assembled the source code in C51ASM. Now we can use both UART and I2C simultaneously. Tested with RDA5807 FM TUNER using both UART and I2C. #BASIC52 #MCS8051

mit41301's tweet photo. We can't use both UART and I2C simultaneously in #CH552E since SDA P1.6 shares with UART.
Reassigned SDA pin to P1.4 and assembled the source code in C51ASM.
Now we can use both UART and I2C simultaneously. Tested with RDA5807 FM TUNER using both UART and I2C.
#BASIC52 #MCS8051 https://t.co/dL7D8jRBJf

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mit41301 @mit41301

over 1 year ago

BASIC-52 running on QMTECH EP4CE15 at 50MHz with Bluetooth serial port 115200 baud. We can easily connect to android or iOS devices. #ASCIIART in 10.58 seconds. Configuration flash EPCS16 used. #intel #BASIC52 #ep4ce15f23 #quartus #vhdl #verilog #systemverilog #mcs8051 #i2c #sfr

mit41301's tweet photo. BASIC-52 running on QMTECH EP4CE15 at 50MHz with Bluetooth serial port 115200 baud.
We can easily connect to android or iOS devices.
#ASCIIART in 10.58 seconds.
Configuration flash EPCS16 used.
#intel #BASIC52 #ep4ce15f23 #quartus #vhdl #verilog #systemverilog #mcs8051 #i2c #sfr https://t.co/4lMyZNC7bp

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mit41301 @mit41301

over 1 year ago

Maximum possible clock for BASIC-52 is 78627473 Hz. MAX10 FPGA 10M08SAU169C8 running BASIC-52 V1.31 at 63MHz. ASCIIART completed in 8.38 seconds. Max1000 oscillator is 12MHz. PLL output 63MHz. #fpga #mcs8051 #max10 #altera #flash #pll #80C52 #BASIC52 #intel #logic #cpld #MCS51

mit41301's tweet photo. Maximum possible clock for BASIC-52 is 78627473 Hz.
MAX10 FPGA 10M08SAU169C8 running BASIC-52 V1.31 at 63MHz.
ASCIIART completed in 8.38 seconds.
Max1000 oscillator is 12MHz. PLL output 63MHz.
#fpga #mcs8051 #max10 #altera #flash #pll #80C52 #BASIC52 #intel #logic #cpld #MCS51 https://t.co/lTmjOZcYP4

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mit41301 @mit41301

over 1 year ago

8052 softcore using CYCLONE IV FPGA #EP4CE6E22C8 running at 48MHz. Running #ASCIIART takes 10.965 seconds. Serial port at 115200 baud on COM17 using USB-TTL. Almost same as CH559 at 48MHz #altera #cyclone #fpga #softcore #MCS51 #mcs8051 #BASIC52 #i2c #intel #ch552 #ch559 #ch558

mit41301's tweet photo. 8052 softcore using CYCLONE IV FPGA #EP4CE6E22C8 running at 48MHz.
Running #ASCIIART takes 10.965 seconds.
Serial port at 115200 baud on COM17 using USB-TTL. Almost same as CH559 at 48MHz
#altera #cyclone #fpga #softcore #MCS51 #mcs8051 #BASIC52 #i2c #intel #ch552 #ch559 #ch558 https://t.co/dCOVjngJhg

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mit41301 @mit41301

about 2 years ago

Dan Karmann’s BASIC-52 Ver 1.2a running on Intel D87C51 with external 8kB EPROM (27C64) and 32kB RAM(62C256). For erasing the internal EPROM we can use single 275nm UVC LED with sticky tape for holding the LED above the quartz window. #intel #87C51 #27C64 #62C256 #BASIC52 #UVC

mit41301's tweet photo. Dan Karmann’s BASIC-52 Ver 1.2a running on Intel D87C51 with external 8kB EPROM (27C64) and 32kB RAM(62C256).
For erasing the internal EPROM we can use single 275nm UVC LED with sticky tape for holding the LED above the quartz window.
#intel #87C51 #27C64 #62C256 #BASIC52 #UVC https://t.co/xzGcEf3kvh

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mit41301 @mit41301

almost 3 years ago

Single chip computer using CH552T with CH551G used as USB-TTL. PORT1 of CH552T tested with interfacing two hexadecimal digits of TIL311 using P1.0~P1.7 Test program just increment and decrease between 0×FF~0×00 #CH552T #CH551G #mcs8051 #basic52 #intel #computer #wchisptool #SBC