#chiselv - Twitter Hashtag

Carlos Eduardo (@[email protected]) @carlosedp

over 4 years ago

Yay, just added support to @DigilentInc Arty A7 to ChiselV thru @OlofKindgren FuseSoc using #SymbiFlow open source FPGA toolchain. #ChiselV #RiscV #FPGA

carlosedp's tweet photo. Yay, just added support to @DigilentInc Arty A7 to ChiselV thru @OlofKindgren FuseSoc using #SymbiFlow open source FPGA toolchain.
#ChiselV #RiscV #FPGA https://t.co/a6ir5ibBM3

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Carlos Eduardo (@[email protected]) @carlosedp

over 4 years ago

Rewriting my RISC-V core, ChiselV as a 5-stage pipelined microarchitecture. Baby steps while making simple ALU ops to work. #RISCV #ChiselV #ChiselHDL

carlosedp's tweet photo. Rewriting my RISC-V core, ChiselV as a 5-stage pipelined microarchitecture.

Baby steps while making simple ALU ops to work.

#RISCV #ChiselV #ChiselHDL https://t.co/R9K5G1vdbf

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Carlos Eduardo (@[email protected]) @carlosedp

over 4 years ago

Happy to say I have a fully working C program running on ChiselV, my RV32I @risc_v processor. Wrote a simple library (like an Arduino) to access the GPIO and Timer. Can’t be more satisfied! 🎉 Now, on to having a serial interface! #RISCV #ChiselV https://t.co/PIHhOcN2Za

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Carlos Eduardo (@[email protected]) @carlosedp

over 4 years ago

Thanks a lot @samsoniuk for helping me out on making ChiselV load/store stalls work! I was stuck on it for a couple days already! Converted his Verilog to a @chisel_lang function that can be called with different latency values. https://t.co/eNAxmkm0Dm #chiselv #FPGA #RISCV

carlosedp's tweet photo. Thanks a lot @samsoniuk for helping me out on making ChiselV load/store stalls work! I was stuck on it for a couple days already!

Converted his Verilog to a @chisel_lang function that can be called with different latency values.

https://t.co/eNAxmkm0Dm
#chiselv #FPGA #RISCV https://t.co/r2tKaRWBhJ

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Carlos Eduardo (@[email protected]) @carlosedp

over 4 years ago

Happy to say that ChiselV, my RISC-V core run a sample LED count assembly program synthesized and loaded using FuseSoc on a FPGA! Never thought I would be do it! 🎉🚀🤓 https://t.co/rQEuL2yPjC @risc_v @RadionaOrg @OlofKindgren @chisel_lang @Calista_Redmond #RISCV #ChiselV

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