Top Tweets for #servingthenextbug

Peter Monsson @SVAssertions

over 2 years ago

Have you integrated Python into an existing #SystemVerilog #UVM testbench? What is the performance overhead? How do you handle communication? TLM? #Verilog #semiconductor #chipdesign #digitalverification #sv #verification #servingthenextbug

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Dave Rich @dave_59

over 3 years ago

Here's a perfect example of the XY Problem on the Verification Academy in action https://t.co/5im5zlNaiI https://t.co/D1EpCYhn9J #verificationengineer #systemverilog #uvm #semiEDA #xyproblem #servingtheNextBug

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Peter Monsson @SVAssertions

almost 4 years ago

🔥 #UVM Debug tip: See all UVM register layer accesses in your simulator log with this function 👇 Call it from your start_of_simulation_phase function in your test. #Verilog #SystemVerilog #semiconductor #chipdesign #digitalverification #sv #servingthenextbug #verification

SVAssertions's tweet photo. 🔥 #UVM Debug tip:

See all UVM register layer accesses in your simulator log with this function 👇

Call it from your start_of_simulation_phase function in your test.

#Verilog #SystemVerilog #semiconductor #chipdesign #digitalverification #sv #servingthenextbug #verification https://t.co/dWHnUUak2W

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