Woohoo! Finally had first compute test succeed on my RDNA2 bring up fork of @__tinygrad__ on mac! π
Now for testing and clean-up:
https://t.co/EpT2Jrwv1u
FYI @m0dm0d
π RDNA2 on Apple Silicon β both paths working!
@ryan_w (OCuLink): Tensor.arange(16) β [0..15] β
Me (TB4/eGPU): Tensor([1,2,3]) β [1 2 3] β
RX 6900 XT + M4 Mac Mini
I made huge progress today with Ryan's fork + my TB4/IOMMU fixes. My SDMA still TODO π§ @__tinygrad__
Following @ryan_w 's lead β running @AnthropicAI Claude + @OpenAI ChatGPT Pro 'extended thinking' as reverse engineering collaborators in the loop.
Genuinely useful combination for live debugging + deep firmware analysis (with my tiny brain & hitting keys in between)!
Some more RDNA2 reverse engineering on Apple M4 via tinygrad π§ Today's findings:
β alloc_sysmem for PSP msg1 buffer appears key on Thunderbolt path
β BAR0 IOMMU registration in custom dext reducing DART crashes
β C2PMSG_81 + C2PMSG_64 behaviour suggests SOS may be executing
Still hitting ring_create rejection (0x8000FFFF) β suspecting Apple's Alpine Ridge TB controller could be a blocker
OCuLink hardware ordered. Testing a direct PCIe path tomorrow π€
@ryan_w@Jimster4801@__tinygrad__ C2PMSG_39 came from AMDRadeonX6000.kext β glad it's useful! ... But you've just given me an idea... to boot up the imac with the 6900 XT attached and try to extract some further info from there.
@ryan_w@Jimster4801@__tinygrad__ That's exactly where we're stuck β SOS silent, C2PMSG_39 = 0x0 for 60s. SYS_DRV not in our sos_fw keys [1, 4, 3]. How did you extract it from the v1_3 array? Happy to share my patch diff and compare notes. I'll get into that and DM
@ryan_w@Jimster4801@__tinygrad__ I've hit a wall today - quite a few areas to explore... BAR0=~0x108ecc000 (dynamic), PSP uses privileged physical mode, bypasses GPU page tables. flush_hdp() is a silent, SOS binary has GlobalPlatform TEE strings β device identity checks that might silently fail.
More RDNA2 findings today exploring @__tinygrad__ BAR0=~0x108ecc000 (dynamic) vs mc_base=0x8000000000 β two different views of the same VRAM. PSP uses privileged physical mode, bypasses GPU page tables. flush_hdp() is a silent no-op on RDNA2 β register doesn't exist.
@__tinygrad__ PSP bootloader wakes β KDB loads β SOS delivered β C2PMSG_39 completely silent β SOS never executes. 60s, nothing.
Advised via discord MC addresses stay on-GPU β so not a DART issue. Address format now confirmed correct. Hardware eliminated. Just stuck on RDNA2 SOS won't fire.
Spent a little time on RDNA2 eGPU support in @__tinygrad__ on Apple Silicon (M4 Mac Mini + RX 6900 XT via Thunderbolt 4).
Big breakthrough: the PSP bootloader IS now waking on cold boot. C2PMSG_35 = 0x80000000 β
Not cracked it yet, have faith Claude will get me there! π§΅1/3
@__tinygrad__ Stuck at _ring_create β GPU DMA to VRAM MC addresses crossing the TB link hits Apple DART IOMMU with no mapping. Most likely need @__tinygrad__ input on VRAM aperture registration.
Progress. π΄
@__tinygrad__ Tomorrowβs explorationβ¦
How do you hand a Thunderbolt eGPU a memory address it can actually read from on Apple Silicon?
The PSP bootloader is alive. It's listening. We just need to point it somewhere it's allowed to look. π
@__tinygrad__ Current blocker: Apple Silicon IOMMU. Bootloader
Accepts the firmware address, tries to DMA from it, Mac locks up hard.
Memory isn't mapped for PCIe access. Next: investigate how @__tinygrad__ 's USB path handles this differently. alloc_sysmem vs palloc. 3/3
@__tinygrad__ Pulled AMD's macOS kext from an iMac running 12.4 β last OS / official RDNA2 eGPU support.
Disassembled AMDRadeonX6000.kext / found queryBootLoaderPostCode() pointing to C2PMSG_39 β previously unread.
Fixed a double-KDB firmware send bug / silently hanging the bootloader. 2/3
@__tinygrad__ Update: past the interrupt controller registers. GPU fully seen and initialised β all 5 firmware files loading. Now hitting PSP bootloader timeout, the last real barrier. RDNA2 init sequence differs from RDNA3. Any pointers on the PSP boot sequence for Navi21?