b a b a

Tech Electronics @ENSAM

[b a b a @mesnavi]

A design from 2009

[arturo182 is on Bluesky now @arturo182]

Advertise your account with one PCB.

I'll start

[Mahesh Venkitachalam @mkvenkit]

AI sucking the joy out of programming is making me turn to retro computers🙂. Here's an interesting 2004 student project from MIT:
The Design and Implementation of the Nintendo Entertainment System.
CPU + PPU + VGA implemented on FPGAs. PDF link:

[HRA!.🅼🆂🆇 @thara1129]

6/7 FPGA MSX

リセット信号関連でタイミング割れが発生してるので、リセット信号を叩いてる FF を分離してみるものの、
分離した新しい方を使っているにもかかわらず、もとからある方に繋がってるようなタイミングエラー表示のままで改善されなかった。
おそらく、論理的に同じだからと、GOWIN EDA が１つに統合してしまうのだろう・・ということで、
「勝手に統合するな！」という指示ができるのか？と Grokさんに聞いてみたら「できる」と教えてくれた。

なんと、コメントに /* synthesis syn_preserve = 1 */ とつければいいらしい。

Grokさんの嘘なんじゃね？と、半分疑いながら試してみたところ、、、正解だったようです。
リセット信号のタイミングエラーが全部解消しました😅
Grokさん、疑ってごめんなさい😖

[ヴァルカン @VulcanIgnis]

New in shrike-gen for @Vicharak_In 's Shrike-lite:

Experimental support for VHDL!

https://t.co/JMLa2mXrfq

Credit: Marco (annoyedmilk) for the VHDL inspiration

@deeempak @AksharVastarpar Is the VHDL blink code correct? Builds fine, haven't tested yet.

#fpga #vhdl #verilog

[Mathematica @mathemetica]

Integration by parts turns products of functions into simpler integrals.

If u(x) and v(x) are continuously differentiable, then ∫u dv = uv − ∫v du.
Use the ILATE rule to pick u: Inverse, Logarithmic, Algebraic, Trigonometric, Exponential.

Example: ∫(log x)⋅1 dx = x log x − x + C.

Engineers rely on it to compute work from variable forces in physics and to solve signals in electrical and mechanical systems.

[tetsuo @tetsuoai]

How CNNs see images.

Tensors, filters, feature maps, stride, padding, channels, pooling, receptive fields, mental model.

[Maria Lipiz @matessindramas]

Así funciona el algoritmo de Dijkstra

[Peter Schmidt-Nielsen @ptrschmdtnlsn]

If you don't want to bother assembling a USB header just to flash your board once, I strongly recommend just putting down 2.54mm through-holes for the USB pins in the standard order (5V, D-, D+, GND), and ordering a super cheap USB->pin header cable.

[Mahesh Venkitachalam @mkvenkit]

Four books for your FPGA journey, in order of increasing complexity:
1. Designing Video Game Hardware in Verilog: Steven Hugg
2. Verilog by Example: Blaine C. Readler
3. Advanced Digital Design with the Verilog HDL: Michael D. Ciletti
4. Advanced FPGA Design: Steve Kilts

[Ian Hanschen @furan]

As a hobbyist, sometimes I’ll choose a component simply because I like the way it looks. CREE CV94A-FGC in PLCC6

[b a b a @mesnavi]

@mithro I bought 2 #fomu fpga from @MouserElec and one of them is not working. The touch buttons are not working. The copper is missing. As you can see in the pictures. Any help!!

[ElectronicsNotes by Ian Poole @ElecNotes]

Solving the Data Center Space Crunch: New 800 VDC Power Designs for AI Infrastructure

In the race to scale AI data centers, every millimeter of board space is critical. As power architectures shift to 800 VDC to support high-performance AI racks like the NVIDIA Kyber architecture, auxiliary power supply design has become a significant bottleneck.

Power Integrations has just announced a major step forward, unveiling two ultra-slim auxiliary PSU reference designs that address these high-voltage challenges head-on.

What makes these designs a game-changer? By leveraging their industry-unique 1700 V PowiGaN™ (Gallium Nitride) single-HEMT technology, they’ve managed to create incredibly dense power solutions that outperform traditional silicon carbide (SiC) approaches:

🔹 Space-Efficient: Freeing up ~30% of space on main power distribution boards (PDBs).
🔹 Simplified BOM: ~30% reduction in component count, boosting overall system reliability.
🔹 High Efficiency: Delivering at least 88% efficiency across line and load.
🔹 Low Profile: Ultra-slim form factors (down to 7mm height) ideal for tight blade-rack architectures.

These designs use InnoMux™-2 ICs to support a nominal 1000 VDC input, providing stable power for the "housekeeping" components—like MCUs, gate drivers, and op-amps—that keep AI systems safe and efficient.

For engineers working on the next generation of AI-ready data center infrastructure, this is a massive leap in simplifying high-voltage design.

#DataCenter #AI #PowerElectronics #GaN #PowerIntegrations #HardwareEngineering #Semiconductors #EnergyEfficiency #NVIDIA #electronicsnotes

[ふくろう @Fukuro_kbLAB]

A Curiously Minty Cyberdeck https://t.co/KpEPDeZgsQ

|v･)あまりにも見覚えがある構成と思ったらやっぱりQMK。
｡oO(しかし凄い所にダイオードねじ込んでますの……)

[Owen Brake @OwenBrakes]

NoLoRa: Team from Edinburgh demonstrated LoRa transmission on MCUs with no radio chips, by utilizing the 27th harmonic of the SPI peripheral

[Greg Steiert @fpgahelper]

It is hard to believe @crowd_supply Teardown 2026 is less than two months away.

They just posted the schedule. In addition to all the great talks planned, you will also have the opportunity to hear me bloviate about how to coerce an RP2350 into loading an FPGA by draging-n-dropping a UF2 file, and proper abuse of the QSPI port.

I look forward to reconnecting with all the regulars and meeting new enthusiasts. Should be another great year.

[Ruth🐾Oyen (ルツ) @Ruth_Oyen]

学生フォロワー層が時々FPGAやりたいとつぶやくのが流れてくるので、MAX V CPLDで安価な学習基板を設計中。
大体の部品配置がきまって、これから配線に入る。

[ANGSUDO @K19Unknown]

https://t.co/9tRnUp063W

[CNX Software @cnxsoft]

Arduino library enabling two-way HD voice over ESP-NOW.
https://t.co/KIOkQuWvL6

The PCMFlow722 library enables (half-duplex) real-time voice over ESP-NOW using the legacy G.722 audio codec on ESP32 boards with a speaker and a microphone, transforming them into walkie-talkies.

A code sample is provided for the @M5Stack Core2 IoT controller that broadcasts audio when pressing the A button, and acts as a receiver otherwise.

[gojimmypi @gojimmypi]

I'm in!

TTGF-UART-FSM-TRNG-Lab ⚙️

This is my first #TinyTapeout ASIC !! My project has a UART with a Finite State Machine: text commands to talk to some shared registers with SPI interface to a True Random Number Generator using a ring oscillator. Testing on the #ULX3S FPGA.

[Pablo T. @controlpaths]

FPGA ♥ Cybersecurity, and cybersecurity needs #FPGA. In this article, I show you the #CryptoliteICE project, an FPGA-based TRNG. This board features an #ICE40 and an RP2040 to generate random numbers with real-time health tests. Check it out!

https://t.co/spWpcIuEK6

[Denis Bodor / @lefinnois.bsky.social @lefinnois]

OMG ! OMG ! OMG !
Linux 6.9 & Buildroot sur une ColorLight 5A-75B hackée avec 32MB de SDRAM et un slot microSD 🥹
(encore du boulot mais on est pas loin d'être tout bon)
#FPGA❤️ #LiteX❤️❤️❤️