A few things need separating here.
Your 0.75µm is almost certainly W2W. W2W does achieve finer alignment — imec has demonstrated 200nm pitch in the lab. But W2W has a hard limit: you cannot screen for known-good dies. Stack too many layers and yield collapses. D2W alignment is roughly 8× worse, but it lets you place only KGD. Yield and scalability are better. That's why the industry is moving D2W to the front line for next-stage scaling.
Production pitch reality: TSMC SoIC at 6µm, Intel Foveros Direct at 9µm, both in high-volume manufacturing in 2025–2026. Huawei's Kirin 9050 Pro at 1.5µm is the finest pitch in any commercial SoC today. You say "it's just a matter of high-volume manufacturing" — right, and high-volume manufacturing is the hardest part.
As for Tau Scaling being nothing new: hybrid bonding isn't new. But making signal propagation time constant τ the system-level optimization target — unifying device, circuit, chip, and system under one metric — that hasn't been done before. It's not a new process. It's a different objective function.
#Huawei #Kirin9050 #LogicFolding #HybridBonding
@TheMagaHulk@Antiworkship It's likely because his income and tax contributions were greater than yours, making him a more attractive candidate for banks to lend money to.