CoNGA'23 update: Event date has been changed to 1-2 March 2023. For participants, you can receive a $150 discount by using the 'NSCC5' discount code for the 'Standard' registration that will allow you to attend the networking event on 28 February and all SCA/HPC Asia sessions!
The CoNGA'23 program committee has been working hard to complete all the reviews but are still facing difficulties due to the upcoming festive season. We have no choice but to delay the acceptance date to 23 Dec 2023. Apologies for any inconvenience.#CoNGA#Posit
It was brought to our attention that the paper submission date was announced as 30 November 2022 on our partner's website. To be fair to everyone, the chairs of CoNGA'23 decided to further extend the paper submission date to 30 November 2022.
https://t.co/zC3rjqqWhY
CoNGA'23: Call for Papers
CoNGA is here again! Please submit your original papers to us by 7 November 2022!
We look forward to meeting you in person in Singapore on 27-28 February 2023!
https://t.co/0b8TuNBKxF
@iamtommythorn @LuciferEvening Thanks for correcting the upper-casing of posits. The quire is perhaps best treated as a vector of 32-bit integers and some software routines that do the extended-precision functions, with hardware support highly optional. The vector should cache well and be cache-size aligned.
@iamtommythorn Studies show the posit multiplier is faster and smaller than an IEEE float multiplier because there are no subnormals. Also, don't multiplier costs grow sort of as ceiling(log2(bitlength))? So a 28-bit significand doesn't cost more logic delays than a 24-bit significand, say.
@iamtommythorn Thanks for the excellent comments, Tommy. The proposed way to add posits to RISC-V was very much a straw man, and I look forward to a better assessment of the cost of the quire. Note: 64-bit posits now have a 1024-bit quire, not 2048. The standard es will be 2, all posit sizes.
Michael Feldman did a fine job of writing up the status of posit arithmetic here:
It received many times the usual number of reads for an article on The Next Platform. It was re-posted on Reddit, Ycombinator, and the Julia langu…https://t.co/F0a83141vx https://t.co/NyxKrdtWE4
@achkasov Yes, Himeshi De Silva at NUS did a study with IEEE binary16, bfloat16, and posit16 for various ML benchmarks. Posit16 did as well as 32-bit IEEE floats; bfloat16 failed to converge for tests with more than 10 categories. Google gets bfloat16 to work by using 32-bit accumulators.
@eschnett Posits support associative multiplication with fused multiply-multiply, fmm(a,b,c), part of the math routine list in the Draft Posit Standard. I've thought about fmmm(a,b,c,d) as well.
Associative addition is supported with the quire. And yes, floats are NOT associative.
Document: PACoGEN: A Hardware Posit Arithmetic Core Generator
By Manish Kumar Jaiswal; Hayden K.-H. So- Published on 5 June 2019
https://t.co/8k119CeG8o