Semiconductor Engineering

Deep Insights For The Tech Industry
#semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #chipdesign #ICmanufacturing

[Semiconductor Engineering @SemiEngineering]

Satellite constellations with extra onboard compute are several steps away from handling full AI workloads for people on Earth.
https://t.co/llduFpvbcR
#datacenters #ODCs #OrbitalDataCenters #radhard
#liquidcooling #semiconductor

[Semiconductor Engineering @SemiEngineering]

A look inside the next-generation AI server rack.
https://t.co/vhbFlqBMuF
#datacenters #AI #3DIC #1MWdatacenters #AIinference @Synopsys #Aitraining

[Semiconductor Engineering @SemiEngineering]

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
https://t.co/luFYBosxAJ

#chiplets #IO #inputoutput #semiconductor

[Semiconductor Engineering @SemiEngineering]

Special Report: Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost. https://t.co/zxAQJe0Wp2
#semiconductor #14A #1nm #CFETs #GAAFETs #2nm
#highnaeuv #processvariation

[Semiconductor Engineering @SemiEngineering]

Chiplets are notoriously expensive and finicky today, and they raise questions about how costs can be managed and reduced. If chiplets are to reach their full potential, those issues will need to be solved. https://t.co/Eu2wlKwOBc
#chiplets #semiconductor

[Semiconductor Engineering @SemiEngineering]

Latest: AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; SiC; DRAM sizing; hybrid bonding ... https://t.co/7fimBm9aF4
#semiconductor #advancedpackaging #ECTC
#HBM

[Semiconductor Engineering @SemiEngineering]

Moving Defect Detection And Classification To The Edge:
Explosion in defectivity requires much faster determination of critical and non-critical defects.https://t.co/thHSLVnxnN
#2nm #semiconductor #edgecomputing #waferinspection

[Semiconductor Engineering @SemiEngineering]

Latest: AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; SiC; DRAM sizing; hybrid bonding ... https://t.co/7fimBm9aF4
#semiconductor #advancedpackaging #ECTC
#HBM

[Semiconductor Engineering @SemiEngineering]

SE's latest Special Report:
Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
https://t.co/BuTbFtFEFN
#AgenticVerification #semiEDA #verification #semiconductor

[Semiconductor Engineering @SemiEngineering]

As high-NA EUV approaches, mask makers need new metrics, model-based checks, and curvilinear-native data flows to keep turn times and defect escapes under control. Part 2 of a roundtable series
https://t.co/rskYvso475
#semiconductor #photomasks #HighNAEUV
#lithography

[Semiconductor Engineering @SemiEngineering]

Chiplets are notoriously expensive and finicky today, and they raise questions about how costs can be managed and reduced. If chiplets are to reach their full potential, those issues will need to be solved. https://t.co/Eu2wlKwOBc
#chiplets #semiconductor

[Semiconductor Engineering @SemiEngineering]

Latest: Taiwan, Europe packaging; 2nm; quantum $; agent honeypots; extreme environment chip design; high-NA EUV; EU flagship power electronics; CNTs; spintronics; HW security &... https://t.co/Xlm33aONpn
#semiconductor #2nm #quantum

[Semiconductor Engineering @SemiEngineering]

New technical papers recently added to Semiconductor Engineering’s library:
https://t.co/ayqBqz9LMe

#semiconductor #siliconphotonics #CFETs #crosstalk #OPAs #functionalsafety #PPA #GAAFETs
#ferroelectric

[Semiconductor Engineering @SemiEngineering]

Latest: Taiwan, Europe packaging; 2nm; quantum $; agent honeypots; extreme environment chip design; high-NA EUV; EU flagship power electronics; CNTs; spintronics; HW security &... https://t.co/Xlm33aONpn
#semiconductor #2nm #quantum

[Semiconductor Engineering @SemiEngineering]

Warpage, heat, and brittleness can cause huge reliability problems for expensive designs.
https://t.co/XpKyHKwOre
#chiplets #solders #photonics #semiconductor

[Semiconductor Engineering @SemiEngineering]

Options Grow For Standardizing Data Movement & Sharing Resources
But figuring out which ones to use, & when to use them, isn’t always clear.
[IMAPS Memory Summit discussion]
https://t.co/jFiIHLiJ8B
@IMAPSorg #semiconductor #CXL #UCIe @Synopsys @intel @SamsungSemiUS @credosemi

[Semiconductor Engineering @SemiEngineering]

Each standard serves a specific use case, so chip architects are choosing more than one for a single design. https://t.co/fLySSJqySt

#semiconductor #interconnects

[Semiconductor Engineering @SemiEngineering]

Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
https://t.co/q8Qom3793y
#semiconductor #interconnects #wires #BPD
#floorplanning #routing

[Semiconductor Engineering @SemiEngineering]

Latest: H200 chips for China? $1.5T IC industry by 2030; HBF; AI memory tools; startup contest; MRC spec; embedding solar chips in windows; high-voltage finFET; automotive DRAM & DFT; photonics deal & $; inference HW; CPU memory module...
https://t.co/UArPCNLURN
#semiconductor

[Semiconductor Engineering @SemiEngineering]

AI agents can be used to identify potential issues during operation and react before it’s too late.
https://t.co/mN1qqYVUdY
#semiconductor #semiEDA #agenticAI