Dmitrii Vasilev

I design the number format, the RTL that runs it, and verify it to silicon (creator of GF and TNF ternary float; on-FPGA training). Also open to AI-agent work.

[Dmitrii Vasilev @t27_dev]

In a two-bit digit alphabet, phi is not observable: a GFTernary dot product is exactly phi² times the same codes read as balanced ternary. The name is not the information. https://t.co/gOVH9xAkgU #NumberFormats

[Dmitrii Vasilev @t27_dev]

Physical width changed the question

A committed-oracle comparison exposed a nominal-width error: TNF16 labelled as 16 bits occupies 19 physical bits, so the table now matches containers before comparing lattices.

https://t.co/pxbZQhT4X4

#NumberFormats #fpga #TNF

[Edmund Humenberger @ico_TC]

The open source tool support for Xilinx FPGAs is growing. Thanks to an awesome community contribution, all Spartan7 FPGAs are now supported in OpenXC7.
https://t.co/r8i2g59bQt

[Dmitrii Vasilev @t27_dev]

@cavearr @ico_TC @hansfbaier This is true!

[Carlos @cavearr]

@ico_TC When I started collaborating with the project this summer, almost by chance, I never imagined I would meet such interesting and intelligent people and, above all, great people. In a way, a feedback loop has emerged that seems unstoppable 🤘 @hansfbaier @t27_dev

[Dmitrii Vasilev @t27_dev]

A bitstream CI job was red for 11 days. Underneath were 13 stacked defects, each hidden by the one above. The repaired flow now emits a 3,822,704-byte XC7A100T bitstream. https://t.co/7VNecYXgeN #FPGA

[Dmitrii Vasilev @t27_dev]

A formal job stayed green while three mechanisms guaranteed it could never go red. Seven repair layers later, fifo and mac produced the repo’s first real z3 verdicts. Need formal that actually runs? https://t.co/UDlLtyXIeu #Formal

[Dmitrii Vasilev @t27_dev]

An apparent 2.1×/2.6× accuracy lead disappeared after equal-stored-width remeasurement. The bug was in the oracle and budget, not the competitor. Need a defensible numeric-format comparison? https://t.co/w6kniSvXXM

[Dmitrii Vasilev @t27_dev]

A repository claimed 512 conformance cases. Zero ran; 412 had neither inputs nor expected values. We replaced the headline count with three honest verdicts: executed, numbered debt, aspirational. https://t.co/opNoR4bssP

[Dmitrii Vasilev @t27_dev]

Ternary’s 5.66% base-economy result is a theorem from a 1950 tube-cost model—not a modern gate benchmark. It can win on the wire and still lose at the gate. Building a custom arithmetic block? https://t.co/8sCOli1fXn

[Dmitrii Vasilev @t27_dev]

Mutation coverage can be wrong when the scanner cannot parse the syntax. This gate had four failure paths—all ternaries—and was scored as fully covered. Need a CI or verification audit? https://t.co/pQ4ZfmY2nM

[Dmitrii Vasilev @t27_dev]

Receipts and coverage seals over a radio mesh

https://t.co/hD4AqTNmNe

#fpga #mesh #meshradio

[Dmitrii Vasilev @t27_dev]

Fifteen measured openXC7 builds show why total build time hides the bottleneck. For small designs, bitstream generation can take as long as—or longer than—place and route.

https://t.co/wzVDJ6RirD #fpga

[Dmitrii Vasilev @t27_dev]

A ratchet counted its compiler’s summary line as another error: 186 reported failures included 25 copies of the tool’s own total. The fix exposed a live emitter defect hidden inside the count.

https://t.co/GGqUrin8Kb #fpga

[Dmitrii Vasilev @t27_dev]

Physical width changed the question. TNF16 was labeled 16-bit but occupies 19 physical bits. Once containers were matched first, the comparison changed—and the tool learned to reject impossible widths.

https://t.co/pxbZQhT4X4 #fpga

[Dmitrii Vasilev @t27_dev]

A gate guarding live documents caught revoked numbers in the exact PR that introduced them—right file, right lines, exit code 1. The PR merged anyway because nobody required the gate.

https://t.co/yRRDvfrGXi #fpga

[Dmitrii Vasilev @t27_dev]

One of four required checks was just a shell command printing a sentence: 20 lines, no logic, green on every PR for months. The test suite it supposedly guarded never blocked a merge.

https://t.co/paWoPIwmUy #fpga

[Dmitrii Vasilev @t27_dev]

A negative control should be written by the person planting the defect it must catch. A boundary mutation operator still found 12 survivors across five gates—six closed by one degenerate-input fixture.

https://t.co/S5teffb87H #fpga

[Dmitrii Vasilev @t27_dev]

Gigabit Ethernet on Artix-7 without a vendor toolchain

#fpga #artix
https://t.co/6mW19AVGX4

[Hans Baier @[email protected] @hansfbaier]

Very important bugfix release of OpenXC7.
Please update!
https://t.co/py7LYb0G5m
Thanks for the community for the great contributions!