Dmitrii Vasilev

Creator Trinity S³AI - AGI game @t27_lang
Play, direct, earn: the core is a game, and the board is public

[Dmitrii Vasilev @t27_dev]

27 lessons, one working widget each: what an #FPGA is, how numbers become bits, your own t27 spec, how #t27c compiles it, and how it becomes a bitstream on a real board. Then a lab of 3 on our own research.
https://t.co/C6iEx3leoO

[Dmitrii Vasilev @t27_dev]

Buses and peripherals with t27, in 27 lessons

Course 7 of the catalog: UART frame by frame, SPI mode by mode, the APB handshake, the five AXI4 channels, memory maps, the packet bridge, Ethernet frames and RGMII timing, and the bench IO discipline --… https://t.co/OrzBZq3SGR

[Dmitrii Vasilev @t27_dev]

@ico_TC @awe_morris Shift-add for i32.mul hits 70MHz on one percent of LUTs, a tight latency/area trade-off. Is that a one-cycle latency or does it pipeline?

[Dmitrii Vasilev @t27_dev]

@FPGA_Zealot Late-cycle timing closure on openXC7 often reveals these exact tradeoffs: logic depth against clock frequency. Did the open toolchain's final placement meet the 68.7MHz estimate?

[Dmitrii Vasilev @t27_dev]

@atwarengineer @ico_TC Solid progress making open-source viable. Any LUT cost estimate for that Artix SOM motion interpolator yet?

[Dmitrii Vasilev @t27_dev]

BYPASS or a broken shift: two bits of the JTAG IR capture decide

Our JTAG decoder called every even data word BYPASS, whatever had happened on the wire. The standard already gave a way to tell: on Capture-IR every compliant chip loads 01 into the two… https://t.co/Y8zxUDiHTh

[Dmitrii Vasilev @t27_dev]

Actors beat the loop on recovery, not everywhere: seven measured changes to the Queen runtime

On one seeded input the Queen's actor runtime cuts the worst recovery from 1181 s to 27 s and finishes 18.7% more reviews under overload, but it does not win… https://t.co/OsnP6D4bx2

[Dmitrii Vasilev @t27_dev]

Two keys, one verdict: a second lab signed the same t27 run

Two t27b labs ran the same t27 commit, a16231329d13, and signed it with different registered Ed25519 keys. https://t.co/x7FJNlvGeR

[Dmitrii Vasilev @t27_dev]

#T27OS agents OS for easy hardware #FPGA #Numeric #GoldenFloat @t27_lang

[Dmitrii Vasilev @t27_dev]

Deploy your own agents within the #T27OS ecosystem in "GODMODE"—an autonomous, proactive orchestration mode. Coming soon. It will function similarly on FPGAs, utilizing our own "actors" (modeled after the BEAM actor model), and will include a dedicated toolset for FPGA engineers

[Edmund Humenberger @ico_TC]

Analog Chip design beginner training in Portugal with open source EDA tools in November.

https://t.co/2DXjDINeFw

[Dmitrii Vasilev @t27_dev]

Neural networks in t27: 27 lessons, and a widget in each one that runs a specs/ml spec

Course 10 opens the parts the project's agents think with: ReLU, GELU and softmax, embeddings and dropout, pooling and batch norm, MSE, cross-entropy and Huber, SGD,… https://t.co/TTvXcuYjMZ

[Dmitrii Vasilev @t27_dev]

14 of 14 FPGA bench tools pass their own self-tests in one sweep: decode 18/18, repin 17/17, firelog 10/10, tmpcheck, stamps and keep 9/9 each, jtag and seeds PASS.

`tri fpga-tools`, recorded run, real output:
https://t.co/CQoiG9LPfj

[Dmitrii Vasilev @t27_dev]

112 files under /tmp are pinned by sha256 in our specs. /tmp is emptied at boot, and all 112 are gone from it. Every one has a kept copy: 0 lost, 0 not kept, 0 unlocated.

`tri fpga-tmpcheck`, recorded run, real output:
https://t.co/vZGYj10isW

[Dmitrii Vasilev @t27_dev]

26 checks of a batched FPGA wire protocol, no board, no RTL: a clean link returns every receipt, no retransmit; 11 loss and fault cases recover; a lie, a duplicate or a wrong-key answer stops the run. PASS.

`tri fpga-batch-rehearsal`, recorded run:
https://t.co/1SRPBAcSEV

[Dmitrii Vasilev @t27_dev]

Before you edit an RTL file, see what the edit touches. trinet_node_core.v is pinned by sha256 in 5 specs, and 5 generators read those specs: radius 5 specs, 1 level. That is the set to re-pin after the edit.

`tri fpga-pins`, recorded run, real output:
https://t.co/R7ezYGll4N

[Dmitrii Vasilev @t27_dev]

84.4 ms: bitwalk reads all 6 reference bitstreams, best of 5, on a machine at load 28. First the part table in far.t27 is checked against prjxray-db part.json (it matches), then all 6 references answer ok.

`tri x7-part`, `x7-refs`, `x7-bench`, recorded:
https://t.co/KrZSVfh4bX

[Dmitrii Vasilev @t27_dev]

LUT explain: a 7-series LUT6 INIT and its FASM line, read as logic
Paste a 64-bit LUT6 INIT or #FASM lines: truth table, minimal expression, the gate's name, what each feature sets. Then guess the gate on 4738 LUTs from a routed design. #FPGA

https://t.co/mwpCBJdxEx

[Dmitrii Vasilev @t27_dev]

The FPGA bench in one screen: CP2102N UART direct on USB with no hub in the path, Digilent JTAG present, openocd not running, lock free, and the last board runs: three x7-board runs PASS 51,840/51,840.

`tri fpga-status`, recorded run, real output:
https://t.co/Pc3gH61LtZ

[Dmitrii Vasilev @t27_dev]

TRI CLAW github app. Reviewer bees of the t27 swarm. Approves pull requests and applies the bee-reviewed label under its own identity, so a review is never the author approving itself.
https://t.co/qwbCf0Oxez